Chip Design Director

📍 Job Overview

Job Title: Chip Design Director

Company: TriEye

Location: Tel Aviv-Yafo, Tel Aviv District, Israel

Job Type: Full-time

Category: Hardware Engineering / Chip Design Management

Date Posted: 2026-04-19T12:39:33

Experience Level: Senior (10+ years)

Remote Status: On-site

🚀 Role Summary

• Lead the architecture, development, and optimization of next-generation SWIR sensors, driving innovation in semiconductor design.

• Manage and mentor a multidisciplinary team of engineers across Analog design, Digital design, and Verification.

• Oversee the complete chip development lifecycle, from initial definition and architecture through to tape-out and production readiness.

• Collaborate with Product and System teams to ensure silicon solutions precisely align with market and product requirements.

• Drive external engagements, including IP definition, procurement, and management of outsourced development activities.

📝 Enhancement Note: This role is positioned as a Director level, implying significant leadership responsibility over a critical R&D function. The focus on "next-generation sensors" and "SWIR sensing technology" indicates a high level of technical challenge and strategic importance within TriEye's core business. The emphasis on managing a multidisciplinary team and overseeing the end-to-end chip development process highlights the need for strong technical acumen combined with robust project and people management skills. The mention of "mass-market adoption" suggests a focus on scalability and cost-effectiveness in design.

📈 Primary Responsibilities

• Architect and lead the end-to-end design of advanced SWIR sensors, translating complex system and product requirements into high-performance silicon solutions.

• Directly manage and guide a multidisciplinary chip design team, fostering a collaborative environment for Analog design, Digital design, and Verification engineers.

• Oversee the entire chip development flow, encompassing planning, scheduling, budgeting, fab interface management, and subcontractor coordination.

• Collaborate closely with Product Management and Systems Engineering to define chip features, high-level architecture, and ensure seamless integration between system behavior and silicon implementation.

• Manage external vendor relationships, including IP definition, procurement, and selection of outsourced development partners, defining Statements of Work (SOWs) and overseeing project execution.

• Partner with Product Engineering teams to facilitate smooth productization, potentially taking broader ownership of product readiness as programs mature.

• Ensure design methodologies, tools, and flows are state-of-the-art, driving continuous improvement in efficiency and quality.

• Contribute to the strategic roadmap for TriEye's sensor technology, identifying opportunities for innovation and competitive advantage.

📝 Enhancement Note: The responsibilities emphasize a blend of technical leadership, team management, and strategic oversight. The "end-to-end chip development" responsibility, coupled with "planning, scheduling, budgeting, fab interface," suggests a need for strong program management skills beyond pure technical design. The explicit mention of managing "external engagements" and "subcontractors" indicates a requirement for vendor management and outsourcing expertise. The collaboration with "Product and System teams" points to the importance of cross-functional communication and alignment with business objectives.

🎓 Skills & Qualifications

Education:

Experience:

• Minimum of 7 years of proven experience in managing multidisciplinary ASIC design teams, successfully leading projects from design inception through tape-outs to production.

• Extensive hands-on experience in either Analog design or Digital design, with a deep understanding of design flows, methodologies, and relevant tools.

Required Skills:

• Chip Architecture & Design Leadership: Proven ability to define and lead chip architecture and overall design for complex ASICs.

• Multidisciplinary Team Management: Extensive experience in managing and mentoring teams comprising Analog designers, Digital designers, and Verification engineers.

• ASIC Design Flows & Methodologies: Deep understanding of end-to-end ASIC development flows, from definition to tape-out and production.

• Analog and/or Digital Design Expertise: Hands-on proficiency in either Analog circuit design or Digital logic design.

• Project Planning & Execution: Strong skills in planning, scheduling, budgeting, and coordinating complex chip development projects.

• Fab Interface & Vendor Management: Experience in managing fab interfaces and coordinating with manufacturing partners, including outsourced development.

• Semiconductor Fundamentals: Solid understanding of semiconductor physics, CMOS technology, and basic FAB processes.

Preferred Skills:

• Image Sensor Design: Specific background or experience in the design of image sensors.

• SWIR Sensing Technology: Familiarity with Short-Wave Infrared (SWIR) sensing principles and applications.

• Nanophotonics & Electro-optical Systems: Understanding of nanophotonics and complete electro-optical system integration.

• Verification Methodologies: Experience with advanced verification strategies and tools.

• Layout Design & Physical Design: Familiarity with IC layout and physical design aspects.

• Productization & Product Engineering: Experience in transitioning designs from R&D to production and working closely with product engineering.

📝 Enhancement Note: The requirement for a "Chip design background" is crucial, and the emphasis on "hands-on experience in Analog design and/or Digital design" suggests that while leadership is key, a strong technical foundation is still expected. The preference for "Image sensors background" directly aligns with TriEye's core product. The "10+" years of AI-derived experience level is a slight adjustment based on the Director title and the "7 years of managing teams" requirement, indicating the need for substantial overall experience in the field.

📊 Process & Systems Portfolio Requirements

Portfolio Essentials:

• Chip Architecture Documentation: Examples of high-level chip architectures designed, outlining key components, interfaces, and design trade-offs.

• Design Flow & Methodology Examples: Demonstrations of established design flows, methodologies, and toolchains used for ASIC development.

• Project Management & Execution: Evidence of successful project planning, scheduling, and budget management for complex chip design projects.

• Team Leadership & Collaboration: Case studies or examples showcasing leadership of multidisciplinary design teams and cross-functional collaboration.

• Problem-Solving & Innovation: Projects highlighting innovative solutions to complex design challenges, process optimization, or performance improvements.

Process Documentation:

• Design Specification & Requirements Traceability: Samples of how system and product requirements are translated into detailed chip specifications and how traceability is maintained throughout the design process.

• Verification Strategy & Test Plans: Examples of comprehensive verification plans and strategies, including coverage metrics and sign-off criteria.

• Tape-out & Post-Silicon Validation: Documentation outlining the tape-out process, characterization plans, and post-silicon validation methodologies.

• Fab Interface & Yield Management: Examples of processes for managing fab interfaces, addressing manufacturing issues, and improving silicon yield.

📝 Enhancement Note: For a Director role, the portfolio should demonstrate not just individual technical contributions but also the ability to lead and structure complex design processes. The focus should be on strategic planning, team enablement, risk management, and successful project delivery, with concrete examples of how these were achieved. Emphasis on documentation of design decisions, verification strategies, and post-silicon activities will be key.

💵 Compensation & Benefits

Salary Range:

The estimated annual base salary for a Chip Design Director in Tel Aviv, Israel, with 10+ years of experience and leadership responsibilities in a high-tech company like TriEye, typically ranges from ₪450,000 to ₪750,000 (approximately $120,000 to $200,000 USD, subject to exchange rates). This range can vary based on specific experience, qualifications, and the company's compensation philosophy.

Benefits:

• Gym Membership: Access to fitness facilities to support employee well-being.

• Parking: Provided parking facilities for convenient commute.

• Cibus Card: A meal voucher or card for daily expenses.

• Generous Vacation: A competitive paid time off policy.

• Team Events: Regular company-sponsored social and team-building activities.

• Stock Options/Equity: Potential for equity participation in a growing tech company.

• Comprehensive Health Insurance: Medical, dental, and vision coverage.

• Professional Development: Opportunities for training, conferences, and continued learning.

Working Hours:

• Standard full-time work week, typically 40 hours. While on-site, TriEye likely offers a professional environment that also supports work-life balance, with potential flexibility for project demands.

📝 Enhancement Note: The salary range is an estimate based on industry benchmarks for senior engineering leadership roles in the Israeli tech sector, considering the company's growth phase and the specialized nature of SWIR technology. Benefits are listed as provided in the input, with additions common for such roles in the Israeli tech market to enhance appeal.

🎯 Team & Company Context

🏢 Company Culture

Industry: Semiconductor / Photonics / Deep Tech (SWIR Sensing)

Company Size: TriEye is a growing company, likely in the range of 50-200 employees, indicating a dynamic environment where individual contributions have a significant impact. This size often balances the agility of a startup with developing structures for larger-scale operations.

Founded: TriEye was founded in 2017, positioning it as a company that has moved beyond the initial startup phase and is now in a significant growth and scaling period, backed by substantial investment. This implies a focus on product development, market penetration, and operational efficiency.

Team Structure:

• R&D Focus: The core of the R&D team is likely structured around specialized engineering disciplines (e.g., Analog, Digital, Systems, Optics, Software).

• Leadership Hierarchy: The Chip Design Director will lead a specific chip design team, reporting to a VP of R&D or CTO. This team will likely be multidisciplinary, requiring strong coordination.

• Cross-functional Collaboration: Close collaboration is expected with Product Management, Systems Engineering, Process Engineering, and potentially Sales/Marketing teams to ensure product-market fit and successful deployment.

Methodology:

• Data-Driven Innovation: Emphasis on leveraging data from simulations, characterization, and field testing to drive design improvements and new product development.

• Agile Development Principles: While core hardware development can be more linear, elements of agile methodologies might be employed for iterative design, verification, and project management.

• Process Optimization: A continuous effort to refine design, verification, and manufacturing processes for efficiency, yield, and cost-effectiveness.

Company Website: www.trieye.tech

📝 Enhancement Note: TriEye's focus on SWIR technology places it in a cutting-edge deep tech sector. The company's recent founding and growth phase suggest an environment that values innovation, rapid execution, and building foundational processes. The "TriEyoneer" culture emphasizes being at the forefront, building unique solutions, and growing with exceptional people.

📈 Career & Growth Analysis

Operations Career Level: This role is at a senior leadership level, often referred to as Director or Head of Chip Design. It involves not only technical expertise but also strategic decision-making, team building, and managing significant R&D budgets and timelines. The scope includes ownership of the entire chip design process for critical product lines.

Reporting Structure: The Chip Design Director will report to a higher-level executive, such as the Chief Technology Officer (CTO) or VP of Engineering. They will lead a team of engineers and potentially managers within their specific domain.

Operations Impact: The Chip Design Director's work directly influences TriEye's core product offering and competitive advantage. Successful chip designs are fundamental to the performance, cost, and scalability of TriEye's SWIR sensors, directly impacting market adoption, revenue generation, and overall company success. Their decisions shape the technological roadmap and innovation pipeline.

Growth Opportunities:

• Technical Specialization: Deepen expertise in SWIR sensor design, nanophotonics, or advanced semiconductor technologies.

• Leadership Expansion: Move into broader R&D leadership roles, such as VP of Engineering or CTO, overseeing multiple engineering disciplines.

• Strategic Product Development: Influence product strategy and roadmap based on technological capabilities and market opportunities.

• Cross-functional Leadership: Gain experience in areas like product management, business development, or operations.

• Industry Influence: Become a recognized expert in SWIR sensing technology through publications, conferences, or industry standards committees.

📝 Enhancement Note: The growth path for a Director of Chip Design often involves managing larger engineering organizations or taking on more strategic product-level responsibilities. The "growth with exceptional people" aspect suggests mentorship and developing future leaders within the team will be a key part of the role.

🌐 Work Environment

Office Type: The description implies a modern, well-equipped office environment designed to foster collaboration and innovation. This is typical for technology companies in Israel focused on R&D and hardware development.

Office Location(s): Modern offices in Tel Aviv with easy access to public transport. This suggests a central, accessible location within a major technology hub, facilitating talent acquisition and employee commutes.

Workspace Context:

• Collaborative Spaces: Likely includes open-plan areas, meeting rooms, and dedicated project spaces to encourage interaction and brainstorming among engineers.

• Advanced Tools & Technology: Access to state-of-the-art design tools, simulation software, lab equipment, and testing facilities necessary for cutting-edge chip design.

• Team Interaction: Opportunities for regular interaction with a multidisciplinary R&D team, fostering a culture of shared learning and problem-solving.

Work Schedule:

• Standard full-time work schedule (approx. 40 hours/week). While the role is on-site, a mature company like TriEye often provides a degree of flexibility to accommodate project needs and work-life balance, especially for senior leadership.

📝 Enhancement Note: The emphasis on "modern offices" and "easy access to public transport" in Tel Aviv points to a desirable and professional work environment, common for attracting top engineering talent in Israel.

📄 Application & Portfolio Review Process

Interview Process:

• Initial Screening: HR or Recruiter call to assess basic qualifications, experience, and cultural fit.

• Hiring Manager Interview: Deep dive into technical expertise, leadership experience, and management style with the hiring manager (likely VP Engineering/CTO).

• Technical Panel Interviews: Sessions with senior engineers and architects to evaluate technical depth in chip architecture, Analog/Digital design, verification, and semiconductor processes.

• Team/Peer Interviews: Meetings with potential direct reports and cross-functional counterparts (e.g., Systems, Product) to assess collaboration and team dynamics.

• Executive Interview: Final discussion with senior leadership to align on strategic vision and long-term fit.

• Portfolio Presentation: A dedicated session where candidates present key projects, design successes, and leadership achievements from their portfolio.

Portfolio Review Tips:

• Showcase Leadership Impact: Focus on projects where you led teams, defined architecture, managed schedules, and drove successful tape-outs. Quantify team size, project scope, and outcomes.

• Highlight Strategic Decisions: Detail the rationale behind architectural choices, design trade-offs, and technology selections. Explain why certain paths were chosen.

• Demonstrate Process Ownership: Present examples of how you established or improved design flows, verification methodologies, or fab interfaces to enhance efficiency and quality.

• Quantify Achievements: Use metrics wherever possible – e.g., performance improvements (%), power reduction (%), yield enhancement (%), schedule adherence (%), team efficiency gains.

• Tailor to SWIR: If possible, include relevant experience with sensors, imaging, or high-speed analog/digital design that translates to SWIR technology.

• Structure for Impact: Organize your portfolio logically, perhaps chronologically or by project type, with clear summaries for each. Prepare a concise presentation narrative.

Challenge Preparation:

• Architecture Design Exercise: Be prepared to discuss how you would approach the architecture for a new SWIR sensor based on hypothetical requirements, considering trade-offs (performance, power, area, cost).

• Team Management Scenarios: Anticipate questions about managing underperforming team members, resolving technical disagreements within the team, or prioritizing competing design tasks.

• Process Improvement Case Study: Be ready to detail a specific instance where you identified a process bottleneck and implemented a solution that yielded measurable improvements in design cycles or quality.

📝 Enhancement Note: The portfolio review for a Director role is crucial. It's not just about technical skills but demonstrating leadership, strategic thinking, and the ability to deliver complex hardware projects. Expect detailed questions about decision-making processes and outcomes.

🛠 Tools & Technology Stack

Primary Tools:

• EDA Tools: Proficiency with industry-standard Electronic Design Automation (EDA) tools for schematic capture, simulation, layout, and physical design. Examples include Cadence Virtuoso, Synopsys Design Compiler, Ansys (for EM simulation), Mentor Graphics (now Siemens EDA) tools.

• Simulation & Modeling: Experience with simulation tools for analog (e.g., SPICE variants like Spectre, Eldo) and digital (e.g., Verilog/VHDL simulators like VCS, Incisive).

• Verification Tools: Familiarity with verification methodologies (e.g., UVM, OVM) and tools for digital verification.

• Layout & Physical Design Tools: Expertise in IC layout editors and tools for place-and-route, timing closure, and physical verification (DRC/LVS).

Analytics & Reporting:

• Design Analysis Tools: Tools for power analysis, timing analysis (e.g., PrimeTime), and signal integrity analysis.

• Data Analysis Platforms: While not directly for chip design, familiarity with platforms for analyzing test results, yield data, and performance metrics is beneficial (e.g., JMP, MATLAB, Python with scientific libraries).

• Project Management Software: Tools like Jira, Asana, or Microsoft Project for tracking design progress, task management, and reporting.

CRM & Automation:

• Not directly applicable to chip design tools, but understanding how the designed chips integrate into larger systems and how product requirements are managed through CRM/PLM systems can be beneficial.

📝 Enhancement Note: The specific EDA tools will vary, but a strong understanding of the types of tools and the design flows they support is critical. The emphasis is on leadership, so familiarity with the latest advancements in EDA and AI-driven design methodologies would be a significant plus.

👥 Team Culture & Values

Operations Values:

• Innovation & Breakthroughs: At the core of TriEye's mission is pushing the boundaries of sensing technology, fostering an environment where novel ideas are encouraged and pursued.

• Ownership & Accountability: TriEyoneers are expected to take full ownership of their work, driving projects to completion and being accountable for outcomes.

• Collaboration & Teamwork: Success relies on effective collaboration across diverse disciplines, valuing diverse perspectives and working together to solve complex problems.

• Excellence & Quality: A commitment to high standards in design, development, and product quality is paramount, ensuring TriEye's technology delivers on its promise.

• Customer Focus: Understanding market needs and customer applications is vital to ensure that technological innovation translates into valuable, market-ready solutions.

Collaboration Style:

• Cross-Functional Integration: Expect close partnerships between chip design, systems engineering, optics, software, and product management to ensure holistic product development.

• Open Communication: A culture that encourages open dialogue, constructive feedback, and knowledge sharing across teams.

• Problem-Solving Focus: Teams likely tackle challenges collaboratively, pooling expertise to overcome technical hurdles efficiently.

• Agile Mindset: While hardware development has its own pace, an agile approach to project management and problem-solving is likely embraced.

📝 Enhancement Note: The company values emphasize a deep-tech, execution-oriented culture. The "TriEyoneer" identity suggests a passionate, driven workforce focused on achieving ambitious goals together.

⚡ Challenges & Growth Opportunities

Challenges:

• Pioneering New Technology: Working with SWIR technology, which is moving from niche to mainstream, presents the challenge of defining new standards, overcoming early adoption hurdles, and scaling production.

• Complex Integration: Integrating advanced nanophotonics with CMOS sensor technology requires sophisticated design and validation, pushing the limits of current capabilities.

• Market Education & Adoption: As SWIR becomes more accessible, there's a need to educate the market about its benefits and drive adoption across diverse applications.

• Talent Acquisition & Retention: Attracting and retaining top-tier engineering talent in a competitive Israeli tech market, especially for highly specialized roles.

• Rapid Scaling: Managing the growth of the R&D team and processes to meet increasing market demand and product development cycles.

Learning & Development Opportunities:

• Deep Dive into SWIR: Gain unparalleled expertise in SWIR sensing, nanophotonics, and advanced semiconductor sensor design.

• Leadership Development: Opportunities to hone leadership, strategic planning, and team management skills within a growing organization.

• Cross-Disciplinary Learning: Exposure to systems engineering, optics, product management, and market dynamics to develop a holistic understanding of the business.

• Industry Impact: Contribute to shaping the future of sensing technology and its applications across critical industries like automotive, defense, and robotics.

• Mentorship: Opportunities to mentor junior engineers and contribute to building the next generation of talent in the field.

📝 Enhancement Note: The challenges highlight the exciting, albeit demanding, nature of working in a frontier technology space. The growth opportunities are significant for individuals looking to make a substantial impact and advance their careers in deep tech leadership.

💡 Interview Preparation

Strategy Questions:

• "Describe your approach to architecting a next-generation SWIR sensor, considering performance, power, and cost trade-offs." (Focus on structured decision-making, understanding of SWIR physics, and market needs).

• "How do you foster a culture of innovation and accountability within a multidisciplinary chip design team?" (Highlight leadership style, motivation techniques, and methods for driving ownership).

• "Walk us through a complex chip design project you led from inception to tape-out. What were the major challenges, and how did you overcome them?" (Be prepared to detail your role, team's contribution, technical hurdles, and project outcomes).

Company & Culture Questions:

• "What excites you most about TriEye's mission and the SWIR sensing market?" (Show genuine interest and understanding of the company's strategic positioning).

• "How would you approach managing external IP vendors or outsourced design partners to ensure quality and timely delivery?" (Demonstrate experience in vendor management, SOW definition, and oversight).

• "Describe your experience with semiconductor fabrication interfaces and managing Fab-related issues." (Highlight understanding of manufacturing constraints and yield optimization).

Portfolio Presentation Strategy:

• Executive Summary First: Start with a high-level overview of your most impactful projects, emphasizing leadership achievements and quantifiable results.

• Deep Dive on Key Projects: Select 2-3 projects that best showcase your experience in architecture, team leadership, and successful tape-outs. For each, cover:

  • Problem/Requirement
  • Your Role & Team Structure
  • Architectural Decisions & Justifications
  • Key Technical Challenges & Solutions
  • Design Flow & Methodologies Used
  • Verification Strategy & Sign-off
  • Tape-out & Post-Silicon Results (performance, yield, power)
  • Lessons Learned & Future Improvements

• Focus on "Why" and "How": Explain the strategic rationale behind your decisions and the practical steps taken to achieve success.

• Metrics are Key: Quantify achievements whenever possible – e.g., "reduced power consumption by X%", "improved signal-to-noise ratio by Y%", "delivered X weeks ahead of schedule."

• Be Prepared for Technical Questions: Anticipate deep dives into specific technical challenges or design choices.

📝 Enhancement Note: The interview process will likely be rigorous, assessing both technical depth and leadership capabilities. The portfolio presentation is a critical component for a Director-level role, serving as the primary vehicle to demonstrate past successes and future potential.

📌 Application Steps

To apply for this Chip Design Director position:

• Submit your application through the Comeet application link provided.

• Portfolio Customization: Curate your resume and any supplementary materials to highlight your experience in leading multidisciplinary ASIC design teams, chip architecture, and end-to-end chip development from inception through tape-out.

• Resume Optimization: Ensure your resume clearly details your years of management experience, specific technical contributions (Analog/Digital design, verification), and successful project deliveries. Use keywords like "ASIC Design Director," "Chip Architecture," "Tape-out," "Semiconductor," and "SWIR" where appropriate.

• Interview Preparation: Practice articulating your leadership philosophy, technical decision-making process, and key project successes. Be ready to discuss your experience with EDA tools, design flows, and fab interfaces.

• Company Research: Familiarize yourself thoroughly with TriEye's technology, market position, and company culture by reviewing their website and recent news. Understand their SWIR sensing approach and target applications.

⚠️ Important Notice: This enhanced job description includes AI-generated insights and operations industry-standard assumptions. All details, especially regarding compensation and specific technical requirements, should be verified directly with TriEye during the application and interview process.