Prototyping Design Software Engineer

📍 Job Overview

Job Title: Prototyping Design Software Engineer

Company: Snap Inc.

Location: Paris, France

Job Type: Full-time

Category: Engineering / Software / Technology

Date Posted: 2026-06-12

Experience Level: 5-10 years

Remote Status: Hybrid (4+ days in office per week)

🚀 Role Summary

• This role focuses on enabling early software development and validation for complex System-on-Chip (SoC) platforms through advanced prototyping and emulation techniques.

• Key responsibilities involve porting RTL designs onto FPGA, HAPS, and ZeBu platforms, and developing low-level embedded software for boot, diagnostics, and interface validation.

• The position requires a strong blend of hardware integration, platform bring-up, and embedded software debugging skills within a fast-paced, cross-functional engineering environment.

• Success in this role hinges on the ability to bridge the gap between hardware RTL and software execution, ensuring seamless platform readiness for pre-silicon validation.

📝 Enhancement Note: This role is highly specialized, focusing on the critical pre-silicon phase of hardware development. It requires a deep understanding of both hardware description languages (HDLs) and embedded software development, with a strong emphasis on platform bring-up and debugging on emulation/prototyping hardware. The "Prototyping Design Software Engineer" title indicates a hybrid role that bridges hardware and software engineering disciplines within the context of SoC development.

📈 Primary Responsibilities

• Port complex SoC and subsystem RTL designs onto FPGA, HAPS, and ZeBu emulation platforms, meticulously managing target-specific code variations to maintain fidelity with ASIC RTL.

• Develop, build, and maintain robust pre-silicon prototyping platforms essential for early firmware development, bootloader (FSBL) bring-up, and validation of critical interfaces (e.g., eMMC, LPDDR, PCIe, MIPI CSI2/DSI, UART, QSPI Flash, SPI, I2C/I3C, GPIO, JTAG).

• Rework RTL, wrappers, and platform-specific logic to optimize for prototyping targets, including HAPS/ZeBu interface PHY adjustments and controller presence management to support common software flows across various pre-silicon environments.

• Develop, integrate, or adapt essential low-level embedded software, including board support code, boot configuration routines, device drivers, diagnostic tools, and RTOS or bare-metal test applications.

• Debug intricate hardware/software bring-up challenges across HAPS, ZeBu, and FPGA targets, encompassing memory-model integration, reset and clock sequencing, controller/PHY interaction, timing issues, waveform analysis, JTAG/SWD debugging, and timing report review.

• Design, develop, and maintain SoC validation tests for pre-tapeout stages utilizing firmware, bare-metal tests, RTOS-based applications, and host automation scripts.

• Collaborate closely with SoC design, verification, infrastructure teams, and external vendors to identify root causes of issues and accelerate pre-silicon software readiness.

• Integrate prototyping platforms into Continuous Integration/Continuous Deployment (CI/CD) workflows, enhancing build reliability, automated regressions, artifact traceability, and shared platform infrastructure.

📝 Enhancement Note: The responsibilities highlight a hands-on role focused on making complex hardware designs functional with software before silicon is available. This involves not just porting code but also actively developing and debugging the software environment that runs on these prototypes. The emphasis on specific interfaces (LPDDR, PCIe, etc.) and debugging tools (JTAG/SWD, waveforms) points to a deep technical requirement.

🎓 Skills & Qualifications

Education: Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a closely related technical field.

Experience: Minimum of 5 years of progressive experience in SoC prototyping, FPGA/emulation bring-up, embedded software development, firmware engineering, or pre-silicon validation.

Required Skills:

• Strong understanding of System-on-Chip (SoC) RTL integration principles and the trade-offs involved in mapping large designs onto prototyping and emulation platforms.

• Hands-on experience with FPGA prototyping and hardware emulation platforms such as Synopsys ZeBu, Synopsys HAPS, or similar environments from Cadence, Siemens, or Synopsys.

• Proficiency in embedded C/C++ and the ability to read, write, and debug low-level firmware for boot sequences, diagnostics, device drivers, and hardware validation.

• Demonstrated experience with RTOS (Real-Time Operating System) concepts and development, including task/thread scheduling, interrupt handling, synchronization mechanisms, timers, memory management, device-driver integration, and adherence to real-time constraints.

• Experience with bare-metal development and boot flows, including boot ROM/FSBL (First Stage Bootloader), startup code, linker scripts, memory maps, MMU/MPU/cache configuration, and Board Support Packages (BSPs).

• Familiarity with ARM Cortex-M/R/A architectures, common SoC peripherals, and essential system interfaces such as LPDDR/DFI, eMMC, PCIe, JTAG/SWD, UART, SPI, I2C/I3C, GPIO, and QSPI Flash.

• Proven ability in debugging complex clocks, resets, timing issues, waveform analysis, platform bring-up problems, and embedded software crashes or assertions across multiple pre-silicon targets.

• Familiarity with debugging tools including JTAG/SWD debuggers, GDB, trace capture, logic analyzers, waveform viewers, embedded logging frameworks, and diagnostic suites.

• Ability to interpret RTL code, hardware schematics, datasheets, and timing reports, and to clearly articulate platform limitations and integration constraints to both hardware and software engineering teams.

• Strong problem-solving capabilities, excellent communication and teamwork skills, and the ability to prioritize tasks effectively in a fast-paced, cross-functional environment. Preferred Skills:

• Experience with Synopsys ZeBu and Synopsys HAPS platforms; experience with other Cadence, Siemens, or Synopsys emulation/prototyping environments is highly advantageous.

• Experience running embedded software, diagnostics, or RTOS-based applications on FPGA or emulator platforms.

• Familiarity with RTOS platforms such as FreeRTOS, Zephyr, ThreadX, QNX, or similar, including BSP/device-driver integration and real-time performance profiling.

• Experience with ARM Cortex-M/R/A architectures, bootloader/FSBL development, memory subsystems (e.g., LPDDR/DFI), and storage or high-speed interfaces like eMMC and PCIe.

• Experience building or maintaining CI/CD pipelines for hardware prototyping and embedded software workflows, utilizing tools like GitLab or TeamCity.

• Experience working closely with system software teams on early boot, FSBL, driver, RTOS, and validation enablement tasks.

• Experience with Static Timing Analysis (STA) for XILINX/Intel FPGA platforms.

📝 Enhancement Note: The qualifications emphasize a blend of hardware and software expertise, crucial for pre-silicon enablement. The minimum requirement of 5+ years and a Master's degree points to a mid-to-senior level role. The preferred qualifications highlight specific tools and platforms that candidates experienced with them will find particularly relevant.

📊 Process & Systems Portfolio Requirements

Portfolio Essentials:

• SoC RTL to Platform Porting Case Study: Showcase a project where you successfully ported complex RTL onto an FPGA, HAPS, or emulation platform. Detail the challenges encountered, the specific adaptations made to the RTL and platform, and the resulting improvements in simulation speed or validation scope.

• Embedded Software Bring-Up Example: Provide an example of bringing up complex embedded software (e.g., bootloader, RTOS, drivers) on a new hardware platform. Include details on debugging boot sequences, peripheral initialization, and demonstrating functionality for critical interfaces.

• Hardware/Software Debugging Documentation: Present a case study demonstrating your ability to debug intricate hardware/software integration issues. This could involve waveform analysis, JTAG/SWD debugging sessions, or root-cause analysis of system crashes on pre-silicon targets. Highlight the methodologies used and the resolution.

• Platform Integration & Automation Showcase: If applicable, include examples of integrating prototyping platforms into CI/CD pipelines or developing automated regression tests. Demonstrate how you improved build reliability, test coverage, or artifact traceability.

Process Documentation:

• Workflow Design & Optimization: Document the process for adapting RTL for prototyping/emulation targets, including managing conditional logic, interface modifications, and ensuring design integrity.

• Software Enablement Process: Outline a systematic approach to developing and integrating low-level embedded software (boot code, drivers, RTOS) for pre-silicon platforms, emphasizing testing and validation strategies.

• Debugging & Root Cause Analysis: Detail a structured process for debugging complex hardware/software interaction issues, from initial symptom identification to root cause analysis and resolution, including the tools and techniques employed.

• Platform Validation & Regression: Describe the process for establishing and maintaining automated validation suites and regression tests for prototyping platforms, ensuring continuous quality assurance.

📝 Enhancement Note: For a role like this, a portfolio is crucial for demonstrating practical experience with complex hardware/software integration. The emphasis should be on showcasing problem-solving skills in debugging and bringing up systems on challenging pre-silicon environments. Quantifiable results, wherever possible, will be highly beneficial.

💵 Compensation & Benefits

Salary Range: Based on industry benchmarks for Prototyping Design Software Engineers with 5-10 years of experience in Paris, France, the estimated annual salary range is €80,000 - €120,000. This estimate considers the specialized nature of the role, the demand for SoC prototyping and embedded software skills, and the cost of living in Paris.

Benefits:

• Paid Parental Leave: Comprehensive support for new parents.

• Medical Coverage: Robust healthcare plans for employees and their families.

• Emotional and Mental Health Support Programs: Access to resources and counseling for well-being.

• Compensation Packages: Competitive salary with potential for stock options or other long-term incentives, allowing employees to share in Snap Inc.'s success.

• Professional Development: Opportunities for continuous learning, training, and attending industry conferences.

• Relocation Assistance: Support for candidates moving to Paris for the role.

Working Hours: Standard full-time working hours are expected, typically around 40 hours per week. While the role requires significant dedication and focus, Snap Inc. promotes a culture where efficient work practices are valued, potentially allowing for some flexibility within the hybrid work model.

📝 Enhancement Note: The salary range is an estimation based on general market data for similar roles in Paris. Actual compensation will be determined by Snap Inc. based on the candidate's specific experience, qualifications, and the company's internal compensation structure. The "Default Together" policy implies a structured office presence, meaning hours are likely tied to office days.

🎯 Team & Company Context

🏢 Company Culture

Industry: Technology, Social Media, Augmented Reality, Hardware Development. Snap Inc. operates at the intersection of cutting-edge software, social connectivity, and innovative hardware, aiming to make computing more human through augmented reality.

Company Size: Snap Inc. is a large, publicly traded technology company with thousands of employees globally. This scale offers significant resources, complex projects, and opportunities for collaboration across diverse teams.

Founded: Snap Inc. was founded in 2011. Its rapid growth and continuous innovation in augmented reality and social communication have established it as a major player in the tech industry.

Team Structure:

• The Prototyping Design Software Engineer will likely be part of a specialized hardware engineering or platform development team within Specs Inc., a subsidiary of Snap Inc.

• This team is expected to be highly collaborative, working closely with SoC RTL designers, verification engineers, system software developers, and infrastructure teams.

• The reporting structure will likely be within a hardware engineering management hierarchy, with direct reporting to a team lead or engineering manager. Methodology:

• Data-Driven Development: Decisions and debugging processes are informed by data from simulations, emulation runs, and real-world testing.

• Agile/Iterative Approach: The rapid pace of innovation suggests an iterative development methodology, with continuous cycles of design, implementation, testing, and refinement.

• Cross-Functional Collaboration: Emphasis on close partnerships with various engineering disciplines to achieve complex technical goals.

Company Website: https://www.snap.com/en-US/

📝 Enhancement Note: Specs Inc. is positioned as the hardware innovation arm, focusing on advanced AR eyewear. This context suggests a culture of pushing boundaries in hardware and software integration, with a strong emphasis on user experience enabled by technology.

📈 Career & Growth Analysis

Operations Career Level: This role is positioned as a mid-to-senior level engineering position. It requires significant technical depth and autonomy in handling complex hardware-software integration tasks on pre-silicon platforms. The "Prototyping Design Software Engineer" title implies a specialized engineering track rather than a traditional operations management path.

Reporting Structure: The engineer will report to a manager or lead within the hardware engineering or platform development group, likely within Specs Inc. Collaboration will extend across multiple engineering teams (RTL, verification, system software, infrastructure).

Operations Impact: While not a traditional "revenue operations" role, this position has a profound impact on the company's ability to deliver innovative hardware products. By enabling early software validation and platform bring-up, this role directly contributes to:

• Accelerated Time-to-Market: Reducing the risk and timeline for hardware development.

• Product Quality & Reliability: Identifying and resolving critical bugs before silicon tape-out.

• Innovation Enablement: Providing the foundation for advanced software features and AR experiences.

Growth Opportunities:

• Technical Specialization: Deepen expertise in SoC prototyping, FPGA/emulation technologies, embedded systems, and specific interface protocols.

• Cross-Functional Leadership: Lead technical initiatives involving multiple engineering disciplines, influencing platform architecture and development strategies.

• Mentorship: Guide junior engineers in hardware-software integration, debugging techniques, and platform bring-up processes.

• Transition to System Architecture: Potentially move into roles focused on defining system-level architecture for future hardware products.

• Exposure to Cutting-Edge AR Tech: Gain deep experience with the development of advanced AR hardware and software platforms.

📝 Enhancement Note: This role offers significant growth potential for engineers passionate about the foundational stages of hardware product development, especially in the emerging field of AR. The impact is less about direct revenue generation and more about enabling the creation of products that drive future revenue and market leadership.

🌐 Work Environment

Office Type: Snap Inc. employs a "default together" policy, indicating a strong emphasis on in-office collaboration. This role is hybrid, requiring employees to work from the Paris office at least 4 days per week. The office environment is designed to foster dynamic collaboration.

Office Location(s): The role is based in Paris, France, specifically at 16 Rue de la Rochefoucauld. This location places the engineer within a major European hub for technology and innovation.

Workspace Context:

• Collaborative Spaces: The office likely features a mix of open-plan work areas, dedicated project rooms, and meeting spaces designed to facilitate brainstorming and problem-solving sessions.

• Advanced Tools & Technology: Access to high-performance workstations, specialized hardware prototyping equipment (FPGA boards, emulators), debugging tools, and robust network infrastructure will be essential for the role.

• Team Interaction: Ample opportunities for direct interaction with colleagues from various engineering disciplines, fostering a culture of shared learning and immediate feedback.

Work Schedule: The hybrid work arrangement, with a minimum of 4 days in the office, is structured to balance focused individual work with collaborative team activities. The specific schedule within the office days may offer some flexibility, but the core requirement is regular in-person engagement.

📝 Enhancement Note: The "default together" policy is a key aspect of Snap's culture, emphasizing in-person synergy for innovation. Candidates should be prepared for a structured hybrid setup that prioritizes team interaction.

📄 Application & Portfolio Review Process

Interview Process:

• Application Submission & Initial Screening: Submit your resume and any requested materials. Recruiters will review for alignment with minimum qualifications.

• Technical Phone Screen: A discussion with an engineer from the hiring team to assess foundational knowledge in SoC, RTL integration, embedded C/C++, and debugging.

Be prepared to discuss past projects and technical challenges.

• On-site/Virtual On-site Interviews: This stage typically involves multiple sessions covering:

  • Deep Technical Dive: In-depth questions on SoC prototyping, FPGA/emulation platforms (ZeBu, HAPS), embedded software development (RTOS, bare-metal), and debugging methodologies.
  • System Design & Problem-Solving: Scenarios requiring you to outline approaches to platform bring-up, debug complex hardware/software issues, or design validation strategies.
  • Portfolio Presentation: A dedicated session to present 1-2 key projects from your portfolio, demonstrating your impact and technical contributions.
  • Behavioral & Team Fit: Questions assessing your collaboration style, problem-solving approach, and how you handle challenges in a fast-paced environment.

• Hiring Manager Interview: Final discussion to assess overall fit, career aspirations, and alignment with the team's goals.

Portfolio Review Tips:

• Prioritize Relevance: Select 1-2 projects that most closely align with the job description, focusing on SoC prototyping, platform bring-up, and embedded software debugging.

• Structure Your Narrative: For each project, clearly articulate the problem statement, your specific role and contributions, the technical challenges faced, the solutions implemented, and the quantifiable outcomes or impact.

• Showcase Technical Depth: Be prepared to walk through code snippets (if appropriate and non-confidential), debugging workflows, waveform analysis, or system diagrams to illustrate your technical expertise.

• Highlight Cross-Functional Collaboration: Demonstrate how you effectively communicated and collaborated with RTL designers, verification engineers, and software teams.

• Prepare for Q&A: Anticipate detailed questions about your design choices, debugging strategies, and problem-solving approaches.

Challenge Preparation:

• SoC Bring-up Scenario: Practice outlining the steps involved in bringing up a complex SoC on an FPGA or emulator, including boot sequences, essential peripheral initialization, and early software validation.

• Debugging Case Study: Prepare to walk through a challenging hardware/software debug scenario you've encountered, detailing your systematic approach, the tools used (JTAG, logic analyzer, waveforms), and how you identified the root cause.

• RTL Adaptation Discussion: Be ready to discuss the considerations and trade-offs when adapting RTL for prototyping platforms, such as managing timing, interface differences, and ensuring software compatibility.

📝 Enhancement Note: The interview process is designed to rigorously evaluate both technical depth and practical problem-solving skills. A strong, well-prepared portfolio demonstrating hands-on experience with the specific technologies mentioned (ZeBu, HAPS, embedded C, RTOS) will be critical for success.

🛠 Tools & Technology Stack

Primary Tools:

• Hardware Emulation/Prototyping Platforms: Synopsys ZeBu, Synopsys HAPS. Experience with Cadence or Siemens equivalents is a plus.

• FPGA Design Tools: Xilinx or Intel FPGA toolchains for synthesis, place-and-route, and timing analysis.

• RTL Design Languages: Verilog/VHDL (implied by SoC RTL integration).

Analytics & Reporting:

• Waveform Viewers: Tools for analyzing signal behavior during simulation and emulation (e.g., Verdi, GTKWave).

• Static Timing Analysis (STA) Tools: For evaluating timing performance on FPGA designs.

• Log Analysis Tools: For parsing and analyzing debug logs from embedded systems.

CRM & Automation:

• Version Control Systems: Git (or similar) for managing RTL and software code.

• CI/CD Tools: GitLab, TeamCity, or similar for automating build, test, and deployment processes for prototyping platforms.

• Debugging Tools: JTAG/SWD debuggers, GDB, trace capture tools, logic analyzers.

📝 Enhancement Note: This stack is highly specific to hardware development and pre-silicon validation. Expertise in these tools, particularly hardware emulation platforms like ZeBu and HAPS, is a defining characteristic of this role and will be heavily scrutinized during the interview process.

👥 Team Culture & Values

Operations Values:

• Innovation & Curiosity: A drive to explore new technologies and push the boundaries of what's possible in AR and hardware.

• Technical Excellence & Rigor: Commitment to high-quality engineering, meticulous debugging, and robust solutions.

• Collaboration & Teamwork: Valuing open communication, knowledge sharing, and mutual support across diverse engineering teams.

• Data-Driven Decision Making: Relying on empirical evidence and analysis to guide development and problem-solving.

• Efficiency & Speed: A focus on optimizing processes and timelines to deliver cutting-edge products rapidly.

Collaboration Style:

• Cross-Functional Integration: Expect a highly collaborative environment where close partnerships between hardware RTL, verification, system software, and infrastructure teams are essential for success.

• Proactive Communication: A culture that encourages open dialogue, early identification of issues, and transparent reporting of progress and roadblocks.

• Knowledge Sharing: Encouragement of sharing best practices, debugging techniques, and platform updates through documentation, internal presentations, or informal discussions.

📝 Enhancement Note: The culture at Snap Inc., particularly within its hardware divisions like Specs Inc., likely emphasizes innovation and speed, balanced with the rigor required for complex hardware development. Collaboration is key, as success hinges on integrating diverse engineering disciplines.

⚡ Challenges & Growth Opportunities

Challenges:

• Complexity of SoC RTL: Managing and porting extremely large and intricate RTL designs onto limited prototyping resources.

• Debugging Hardware/Software Interactions: Pinpointing root causes of bugs that span both hardware and software layers on complex, pre-silicon platforms.

• Rapid Technology Evolution: Keeping pace with advancements in emulation technology, FPGA capabilities, and embedded software practices.

• Balancing Fidelity and Performance: Ensuring the prototyping platform accurately reflects ASIC behavior while achieving acceptable performance for software validation.

• Cross-Team Dependencies: Navigating dependencies with multiple teams (RTL, verification, system software) to achieve platform readiness.

Learning & Development Opportunities:

• Advanced Emulation/Prototyping Techniques: Deep dive into state-of-the-art methodologies for SoC prototyping and hardware emulation.

• Embedded Systems Expertise: Expand knowledge in RTOS, bare-metal programming, device drivers, and low-level system architecture.

• AR Hardware & Software Integration: Gain unique insights into the development of cutting-edge augmented reality hardware and its software ecosystem.

• Industry Conferences & Training: Opportunities to attend relevant conferences and specialized training programs to stay abreast of industry advancements.

• Mentorship from Senior Engineers: Learning from experienced professionals in SoC design, emulation, and embedded systems engineering.

📝 Enhancement Note: This role presents significant technical challenges that are also immense growth opportunities. Overcoming these challenges will build highly specialized and in-demand skills within the semiconductor and advanced hardware development industries.

💡 Interview Preparation

Strategy Questions:

• SoC Platform Bring-Up Strategy: "Describe your systematic approach to bringing up a new, complex SoC on an FPGA or emulation platform for the first time. What are the key phases, critical interfaces, and potential pitfalls?" (Focus on boot flow, essential drivers, validation strategy).

• Hardware/Software Debugging Methodology: "Walk me through a time you faced a challenging bug that involved both hardware and software. How did you approach isolating the root cause? What tools did you use, and what was the resolution?" (Emphasize systematic debugging, waveform analysis, JTAG/SWD usage).

• RTL Adaptation for Prototyping: "When porting RTL to an FPGA or emulation platform, what are the primary considerations and trade-offs you need to manage? How do you ensure the platform remains representative of the ASIC design?" (Discuss timing, interface differences, conditional logic).

Company & Culture Questions:

• "Why Snap Inc. and Specs Inc.?" Research Snap's mission, AR initiatives, and Specs Inc.'s role in hardware innovation. Connect your passion for this technology to their vision.

• "How do you approach collaboration in a fast-paced, cross-functional environment?" Discuss your experience working with different engineering teams and how you ensure effective communication and alignment.

• "How do you handle ambiguity or rapidly changing requirements in a project?" Relate this to your experience in pre-silicon development where requirements can evolve. Portfolio Presentation Strategy:

• Tell a Story: Structure your portfolio presentation like a narrative: problem, your solution, challenges, and impact.

• Show, Don't Just Tell: Use diagrams, screenshots of waveforms, or code snippets (if permissible) to illustrate your technical contributions.

• Quantify Impact: Wherever possible, provide metrics on performance improvements, bug reduction, or time saved.

• Focus on "Your" Role: Clearly articulate your specific contributions, even within a team project.

• Be Prepared for Deep Dives: Anticipate technical questions about every aspect of your presented projects.

📝 Enhancement Note: The interview process will heavily test your practical experience and problem-solving skills. Be ready to demonstrate not just knowledge but the ability to apply it in complex, real-world scenarios relevant to SoC development and pre-silicon validation.

📌 Application Steps

To apply for this Prototyping Design Software Engineer position:

• Submit your application through the provided Workday link.

• Tailor Your Resume: Highlight keywords and experiences directly related to SoC prototyping, FPGA/emulation platforms (ZeBu, HAPS), embedded C/C++, RTOS, bare-metal development, and hardware/software debugging. Quantify achievements where possible.

• Prepare Your Portfolio: Select 1-2 impactful projects that showcase your expertise in the core responsibilities. Ensure you can clearly articulate the technical details, your role, challenges, and outcomes. Practice presenting these projects concisely and effectively.

• Research Snap Inc. and Specs Inc.: Understand their mission, products (Snapchat, Lens Studio, Spectacles), and their focus on augmented reality and human-centric computing. Be ready to articulate why you're excited about contributing to their specific technological pursuits.

• Practice Technical Interview Questions: Review common interview topics for hardware/software integration roles, focusing on SoC architecture, debugging methodologies, and specific tool proficiencies.

⚠️ Important Notice: This enhanced job description includes AI-generated insights and operations industry-standard assumptions. All details should be verified directly with the hiring organization before making application decisions.