Prototyping Design Software Engineer

📍 Job Overview

Job Title: Prototyping Design Software Engineer

Company: Snap Inc.

Location: Paris, France

Job Type: Full-time

Category: Hardware Engineering / Embedded Software

Date Posted: 2026-06-12

Experience Level: 5-10 years

Remote Status: Hybrid (4+ days in office)

🚀 Role Summary

• Spearhead the integration of complex System-on-Chip (SoC) RTL onto FPGA, HAPS, and ZeBu prototyping platforms to facilitate early software development and validation.

• Develop and maintain robust pre-silicon platforms, enabling critical boot flows, firmware development, and validation of key hardware interfaces.

• Drive low-level embedded software development, including bootloaders, device drivers, and RTOS/bare-metal applications, for seamless platform bring-up.

• Debug intricate hardware-software integration issues across diverse pre-silicon environments, ensuring platform stability and functionality.

• Collaborate closely with RTL, verification, system software, and infrastructure teams to accelerate pre-silicon software readiness and optimize the overall development lifecycle.

📝 Enhancement Note: This role is highly specialized, focusing on the critical intersection of hardware prototyping and embedded software development for advanced SoC designs. The emphasis on pre-silicon validation and platform bring-up indicates a need for deep technical expertise in both hardware description languages and low-level software. The "Prototyping Design Software Engineer" title suggests a hybrid role that bridges traditional hardware design verification with embedded systems engineering.

📈 Primary Responsibilities

• Port complex System-on-Chip (SoC) and subsystem RTL onto FPGA, HAPS, and ZeBu platforms, ensuring fidelity to ASIC RTL while managing platform-specific adaptations.

• Construct and maintain pre-silicon platforms to support early firmware, bootloader (FSBL), and critical interface validation (eMMC, LPDDR, PCIe, MIPI CSI2/DSI, UART, QSPI Flash, SPI, I2C/I3C, GPIO, JTAG).

• Rework RTL, wrappers, and platform-specific logic to optimize for prototyping targets, including HAPS/ZeBu interface PHY modifications and controller presence management for common software flows.

• Develop, integrate, and adapt essential low-level embedded software for platform bring-up, such as board support code, boot configurations, diagnostic routines, and RTOS or bare-metal test applications.

• Debug complex hardware/software bring-up challenges on HAPS, ZeBu, and FPGA targets, encompassing memory-model integration, reset/clock sequencing, controller/PHY interaction, timing analysis, waveform interpretation, JTAG/SWD debug, and timing report reviews.

• Design, develop, and maintain SoC validation tests for pre-tapeout stages utilizing firmware, bare-metal tests, RTOS-based applications, and host automation frameworks.

• Collaborate with SoC design, verification, infrastructure teams, and external vendors to address issues and expedite pre-silicon software readiness.

• Integrate prototyping platforms into Continuous Integration/Continuous Deployment (CI/CD) pipelines, enhancing build reliability, automated regressions, artifact traceability, and shared platform infrastructure.

📝 Enhancement Note: The responsibilities highlight a hands-on role requiring deep technical skills in both hardware description languages (RTL) and embedded software development. The focus on specific interfaces like LPDDR, PCIe, and MIPI CSI2/DSI indicates the complexity and cutting-edge nature of the SoC designs being worked on. The integration into CI/CD flows points towards modern development practices being employed.

🎓 Skills & Qualifications

Education: Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a closely related field.

Experience: 5+ years of progressive experience in SoC prototyping, FPGA/emulation bring-up, embedded software development, firmware engineering, or pre-silicon validation.

Required Skills:

• Strong understanding of SoC RTL integration and the trade-offs inherent in mapping large designs onto prototyping and emulation platforms.

• Hands-on experience with FPGA prototyping and hardware emulation platforms such as HAPS, ZeBu, or similar Cadence/Siemens/Synopsys environments.

• Proficiency in embedded C/C++ with the ability to read, write, and debug low-level firmware for boot, diagnostics, drivers, and hardware validation.

• Experience with RTOS (Real-Time Operating System) concepts and development, including task scheduling, interrupts, synchronization, timers, memory management, device-driver integration, and real-time constraints.

• Experience with bare-metal development and boot flows, including boot ROM/FSBL, startup code, linker scripts, memory maps, MMU/MPU/cache configuration, and board support packages (BSPs).

• Familiarity with ARM Cortex-M/R/A architectures, common SoC peripherals, and system interfaces such as LPDDR/DFI, eMMC, PCIe, JTAG/SWD, UART, SPI, I2C/I3C, GPIO, and QSPI Flash.

• Proven experience debugging clocks, resets, timing issues, waveforms, platform bring-up problems, and embedded software crashes or asserts across multiple pre-silicon targets.

• Familiarity with debugging tools including JTAG/SWD, GDB, trace tools, logic analyzers, waveform viewers, embedded logging, and diagnostic frameworks.

• Ability to interpret RTL, hardware schematics, datasheets, and timing reports, and to clearly communicate platform limitations and integration constraints to cross-functional hardware and software teams.

• Strong problem-solving, communication, teamwork, and prioritization skills within a fast-paced, cross-functional environment. Preferred Skills:

• Experience with Synopsys ZeBu and Synopsys HAPS platforms; familiarity with other Cadence, Siemens, or Synopsys emulation/prototyping environments is advantageous.

• Experience running embedded software, diagnostics, or RTOS-based applications on FPGA or emulator platforms.

• Experience with RTOS platforms such as FreeRTOS, Zephyr, ThreadX, QNX, or similar, including BSP/device-driver integration and real-time profiling.

• Experience with ARM Cortex-M/R/A architectures, bootloader/FSBL development, memory subsystems like LPDDR/DFI, and storage or high-speed interfaces such as eMMC and PCIe.

• Experience building or maintaining CI/CD pipelines for hardware prototyping and embedded software flows (e.g., GitLab, TeamCity).

• Experience working closely with system software teams on early boot, FSBL, driver, RTOS, and validation enablement.

• Experience with Static Timing Analysis for XILINX/Intel FPGA platforms.

📝 Enhancement Note: The "Minimum Qualifications" and "Preferred Qualifications" sections clearly delineate the core competencies and desired advanced skills. The emphasis on specific platforms (HAPS, ZeBu) and interfaces (LPDDR, PCIe) suggests the company is working with high-performance, complex hardware. The inclusion of static timing analysis as a preferred skill indicates a need for attention to detail regarding performance and timing constraints.

📊 Process & Systems Portfolio Requirements

Portfolio Essentials:

• Evidence of successful SoC RTL porting to FPGA/emulation platforms, demonstrating an understanding of RTL constraints and optimization strategies for prototyping environments.

• Case studies showcasing the bring-up of complex embedded systems, detailing challenges faced in boot process, driver development, and hardware-software interface debugging.

• Examples of low-level embedded software (bare-metal or RTOS) developed for hardware validation, highlighting proficiency in C/C++ and direct hardware interaction.

• Documentation or presentation of debugging methodologies used for complex hardware/software integration issues, including waveform analysis, JTAG/SWD debugging, and issue root-cause determination. Process Documentation:

• Showcase of experience in developing and maintaining board support packages (BSPs) and boot firmware (FSBL), illustrating a structured approach to system initialization.

• Examples of integrating and debugging device drivers for various SoC peripherals (e.g., memory controllers, communication interfaces), demonstrating a systematic testing and validation process.

• Demonstrations of how you've contributed to or built CI/CD pipelines for hardware prototyping or embedded software, emphasizing automation, regression testing, and artifact management.

• Documentation of collaboration processes with RTL, verification, and system software teams, illustrating effective communication and problem-solving strategies for pre-silicon readiness.

📝 Enhancement Note: For a role like this, a portfolio would ideally showcase not just code, but also the process and challenges involved in complex hardware-software integration. Demonstrating the ability to debug at a low level, understand RTL constraints, and work within a structured development and validation framework is crucial. The emphasis is on practical application and problem-solving in a pre-silicon context.

💵 Compensation & Benefits

Salary Range: Based on experience level (5-10 years), location (Paris, France), and the specialized nature of the role (SoC Prototyping, Embedded Software), an estimated annual gross salary range would be €70,000 - €100,000. This estimate is derived from industry benchmarks for Senior Hardware/Embedded Software Engineers in major European tech hubs, considering the high demand for expertise in FPGA prototyping and pre-silicon validation.

Benefits:

• Paid Parental Leave: Comprehensive support for new parents.

• Comprehensive Medical Coverage: Robust health insurance plans for employees and their families.

• Emotional and Mental Health Support Programs: Access to resources and services for well-being.

• Compensation Packages: Competitive salary, potentially including stock options or other long-term incentives reflecting Snap Inc.'s success.

• Hybrid Work Model: Flexibility with a structured "default together" approach, requiring 4+ days in the office.

Working Hours: Standard full-time working hours, typically around 40 hours per week, with the expectation of flexibility to meet project deadlines and critical bring-up phases.

📝 Enhancement Note: Salary estimation for specialized engineering roles in Paris can vary significantly. The provided range is a benchmark, and the actual compensation will depend on the candidate's specific experience, negotiation skills, and Snap Inc.'s internal compensation bands. The benefits package is typical for large tech companies, with a notable emphasis on employee well-being and long-term incentives. The "default together" policy implies a structured hybrid environment.

🎯 Team & Company Context

🏢 Company Culture

Industry: Technology, Social Media, Augmented Reality (AR), Hardware Development. Snap Inc. is at the forefront of developing innovative camera-centric technologies and AR experiences, with Specs Inc. focusing on advanced AR eyewear.

Company Size: Snap Inc. is a large, publicly traded technology company with thousands of employees globally. Specs Inc., as a subsidiary, likely operates with a dedicated team but benefits from the resources of its parent company.

Founded: Snap Inc. was founded in 2011. Specs Inc. is a newer venture focused on hardware innovation. This history suggests a culture that values rapid innovation, experimentation, and pushing technological boundaries.

Team Structure:

• The Prototyping Design Software Engineer will likely be part of a specialized hardware engineering or platform development team within Specs Inc. or a related division at Snap Inc.

• Reporting structure will likely be to an Engineering Manager or Director overseeing hardware prototyping, emulation, or pre-silicon validation efforts.

• Cross-functional collaboration is essential, involving close partnerships with RTL design engineers, verification engineers, system software developers, firmware engineers, and potentially infrastructure/toolchain specialists. Methodology:

• Data-driven decision-making is core to Snap Inc.'s philosophy, applied here through rigorous testing, debugging, and performance analysis of hardware and software.

• Workflow optimization is critical, focusing on efficient porting of RTL, enabling smooth software bring-up, and streamlining the overall pre-silicon validation process.

• Automation and efficiency practices are paramount, especially with the emphasis on integrating platforms into CI/CD flows and developing automated regression tests.

Company Website: https://www.snap.com/en-US/

📝 Enhancement Note: The company culture at Snap Inc. is known for being fast-paced, creative, and focused on user experience and innovation. For this role, expect a highly technical and collaborative environment where pushing the boundaries of AR hardware and software is the norm. The "default together" policy indicates a strong emphasis on in-person collaboration.

📈 Career & Growth Analysis

Operations Career Level: This role is positioned as a Senior Engineer, requiring significant hands-on experience and the ability to work independently on complex technical challenges. It’s a hands-on technical contributor role, not a management track, but offers opportunities for deep specialization.

Reporting Structure: The engineer will report to a manager responsible for hardware prototyping or pre-silicon validation. The role requires significant collaboration with peer engineers and leads across different functional teams (RTL, verification, software).

Operations Impact: This role has a direct and critical impact on the product development lifecycle. By enabling early software development and validation on pre-silicon platforms, this engineer significantly accelerates time-to-market for Snap Inc.'s advanced AR hardware (Specs). Their work directly influences the quality, stability, and performance of the final product by identifying and resolving critical hardware-software integration issues before silicon is available.

Growth Opportunities:

• Deep Technical Specialization: Become a go-to expert in SoC prototyping, FPGA/emulation bring-up, and embedded firmware for advanced AR hardware.

• Cross-Functional Leadership: Lead technical initiatives and mentor junior engineers in hardware-software integration and pre-silicon validation methodologies.

• Exposure to Cutting-Edge Technology: Work with state-of-the-art AR hardware, custom silicon, and advanced development tools, staying at the forefront of the industry.

• Career Advancement: Potential progression to Staff or Principal Engineer roles, or specialized architect positions within hardware or systems engineering.

📝 Enhancement Note: The growth path for this role emphasizes technical depth rather than management. Candidates who excel here can become highly sought-after specialists in a niche but critical area of hardware development. The exposure to Snap's AR initiatives offers a unique opportunity to shape future consumer technology.

🌐 Work Environment

Office Type: The role is hybrid, with a "default together" policy requiring employees to work in the office at least 4 days per week. This suggests a collaborative office environment designed to foster in-person interaction and teamwork.

Office Location(s): The specific office is located in Paris, France, at 16 Rue de la Rochefoucauld. This location will serve as the primary base for in-office workdays.

Workspace Context:

• The workspace will likely be equipped with high-performance computing resources necessary for RTL simulation, FPGA development, and embedded software debugging.

• Expect access to specialized hardware development tools, logic analyzers, oscilloscopes, and debugging interfaces (JTAG/SWD).

• Collaborative spaces, meeting rooms, and potentially dedicated lab areas for hardware bring-up will be available to facilitate teamwork and hands-on problem-solving.

• The environment is expected to be dynamic and fast-paced, typical of a leading technology company focused on rapid product development.

Work Schedule: Standard professional work hours (approximately 40 hours/week) are expected, with flexibility to accommodate critical project phases, such as platform bring-up or pre-tapeout validation cycles. This may involve occasional extended hours or weekend work during intense periods, balanced by the hybrid work arrangement.

📝 Enhancement Note: The "default together" policy is a key aspect of Snap's work environment, indicating a strong preference for in-person collaboration. This means candidates should be comfortable working from the Paris office for the majority of the week and actively participating in team activities and discussions.

📄 Application & Portfolio Review Process

Interview Process:

• Initial Screening: A recruiter or hiring manager will likely conduct a brief call to assess basic qualifications, experience, and cultural fit.

• Technical Phone/Video Interview(s): Expect 1-2 interviews focusing on core technical skills. This may include:

  • Deep dives into your experience with SoC prototyping, FPGA/emulation, and embedded C/C++.

• Hypothetical scenarios involving debugging hardware/software issues or bringing up specific interfaces.

• Questions about RTOS concepts, boot flows, and ARM architecture.

• Discussion of your past projects and contributions.

• On-site (or Virtual On-site) Loop: This typically involves several back-to-back interviews with different team members, including:

  • Technical Deep Dive: More in-depth problem-solving, coding challenges (embedded C/C++), and system-level design discussions.
  • Portfolio Review: A dedicated session to present and discuss your portfolio, highlighting specific projects, challenges, and solutions.
  • Cross-functional Collaboration: Interviews with engineers from RTL, verification, or software teams to assess teamwork and communication skills.
  • Manager/Director Interview: Focus on career aspirations, leadership potential, problem-solving approach, and cultural alignment.

• Final Round/Offer: Discussions with senior leadership and final offer negotiation.

Portfolio Review Tips:

• Highlight Relevance: Focus on projects directly related to

SoC prototyping, FPGA/emulation, embedded C/C++ development, RTOS, bare-metal programming, and hardware-software debugging.

• Structure Your Projects: For each project, clearly outline:

  • The problem or objective.
  • Your specific role and contributions.
  • The technologies and tools used (e.g., HAPS, ZeBu, specific RTL, C/C++, RTOS).
  • The challenges encountered and how you overcame them.
  • The outcomes and impact (e.g., successful bring-up, reduced debug time, improved stability).

• Demonstrate Debugging Skills: Showcase examples of complex issues you've diagnosed and resolved, detailing your methodology (waveforms, JTAG, logs, etc.).

• Code Samples: Be prepared to walk through relevant code snippets, explaining design choices and low-level implementation details.

• Process & Methodology: Explain your approach to system design, documentation, and collaboration.

• Conciseness: Be prepared to present your most impactful work efficiently.

Challenge Preparation:

• Embedded C/C++: Practice coding challenges involving bit manipulation, memory management, interrupt handling, and driver implementation.

• System Design: Be ready to discuss how you would approach bringing up a new SoC on an FPGA, including key interfaces and potential pitfalls.

• Debugging Scenarios: Prepare to analyze hypothetical debugging scenarios involving clock/reset issues, bus contention, or software crashes.

• RTL Understanding: Be able to discuss your experience with RTL and how you adapt it for prototyping.

• RTOS Concepts: Review task scheduling, inter-process communication, memory protection, and device driver integration within an RTOS context.

📝 Enhancement Note: The interview process for such a specialized role will be rigorous, focusing heavily on practical, hands-on technical skills and problem-solving abilities. A well-prepared portfolio that clearly demonstrates relevant experience is crucial for success.

🛠 Tools & Technology Stack

Primary Tools:

• Prototyping/Emulation Platforms: Synopsys ZeBu, Synopsys HAPS, FPGA development environments (e.g., Xilinx Vivado, Intel Quartus).

• Hardware Description Languages (HDLs): Verilog, VHDL (for understanding and potentially modifying RTL).

• Embedded Software Development: C/C++, ARM Assembly (for low-level code).

• Debugging Tools: JTAG/SWD debuggers (e.g., Lauterbach, P&E), GDB, Trace tools, Logic Analyzers, Oscilloscopes, Waveform viewers.

• Version Control: Git.

Analytics & Reporting:

• While not directly analytics-focused, understanding performance metrics from prototypes and debug logs is key. Tools like waveform viewers and logging frameworks are essential for data analysis. CRM & Automation:

• CI/CD Tools: GitLab CI, TeamCity, Jenkins (for integrating prototyping platforms and automating build/test flows).

• Scripting: Python, Shell scripting (for automation tasks, build scripts, and test harnesses).

• RTOS: FreeRTOS, Zephyr, ThreadX, QNX, or similar real-time operating systems.

📝 Enhancement Note: Proficiency with specific emulation platforms like ZeBu and HAPS, along with deep embedded C/C++ skills and debugging tools, are critical requirements for this role. Experience with CI/CD for hardware/embedded software is a significant plus, indicating modern development practices.

👥 Team Culture & Values

Operations Values:

• Innovation & Experimentation: A culture that encourages pushing technological boundaries, especially in AR and hardware design.

• Data-Driven Approach: Decisions are informed by rigorous testing, analysis of debug data, and performance metrics from prototypes.

• Collaboration & Teamwork: Strong emphasis on working together across hardware and software disciplines to achieve common goals.

• Efficiency & Optimization: Continuous effort to improve processes, streamline workflows, and enhance the reliability and speed of development cycles.

• Excellence in Execution: A commitment to high-quality work, meticulous debugging, and delivering robust solutions in a fast-paced environment.

Collaboration Style:

• Cross-functional Integration: Expect to work closely with diverse engineering teams (RTL, verification, system software), requiring clear communication and mutual understanding of different domains.

• Process Review & Feedback: An open environment where methodologies and approaches are discussed, reviewed, and improved collaboratively.

• Knowledge Sharing: Encouragement of sharing insights, debugging techniques, and best practices across teams to accelerate collective learning and problem-solving.

📝 Enhancement Note: The values emphasize a blend of cutting-edge innovation and disciplined execution. Collaboration is key, bridging the gap between hardware design and software implementation, which is essential for successful SoC prototyping and bring-up.

⚡ Challenges & Growth Opportunities

Challenges:

• Complexity of SoC Designs: Working with increasingly complex and large-scale SoC RTL that push the limits of current FPGA and emulation technologies.

• Hardware/Software Debugging: Diagnosing and resolving intricate issues that span both hardware logic and low-level software execution on pre-silicon platforms.

• Platform Maintenance & Evolution: Keeping prototyping platforms synchronized with evolving ASIC RTL and enabling new features and interfaces while maintaining stability.

• Rapid Development Cycles: Meeting aggressive timelines for pre-silicon software readiness in a fast-paced product development environment.

• Cross-Disciplinary Communication: Effectively bridging the communication gap between hardware RTL engineers and software developers.

Learning & Development Opportunities:

• Advanced Prototyping & Emulation: Deepen expertise in state-of-the-art FPGA and hardware emulation technologies and methodologies.

• Cutting-Edge AR Hardware: Gain hands-on experience with the development of advanced AR eyewear and related silicon.

• Embedded Systems Expertise: Expand knowledge in RTOS, bootloaders, device drivers, and low-level firmware for complex architectures.

• Industry Best Practices: Learn and implement best practices in pre-silicon validation, CI/CD for hardware, and hardware-software co-design.

• Mentorship: Opportunities to learn from experienced engineers and potentially mentor junior team members as you grow in the role.

📝 Enhancement Note: This role offers significant challenges that are directly tied to learning and growth. Overcoming complex technical hurdles in a cutting-edge field provides substantial opportunities for professional development and specialization.

💡 Interview Preparation

Strategy Questions:

• "Describe a complex hardware/software integration issue you faced during platform bring-up. What was your methodology for debugging it, and what was the resolution?" (Focus on structured debugging, waveform analysis, JTAG/SWD, and root cause analysis.)

• "How would you approach porting a large SoC RTL design to an FPGA platform, considering timing, resource utilization, and maintainability for software development?" (Emphasize trade-offs, platform-specific adaptations, and keeping RTL close to ASIC.)

• "Explain the process of bringing up a bootloader (FSBL) on a new embedded system. What are the critical components and potential challenges?" (Detail boot ROM, configuration, memory initialization, and peripheral setup.)

• "How do you ensure your embedded C/C++ code is robust and efficient for low-level firmware development, especially concerning memory management and interrupt handling?" (Discuss coding standards, optimization techniques, and defensive programming.)

• "Describe your experience with RTOS concepts. How would you integrate a new device driver into an RTOS, and what considerations are important for real-time performance?" (Focus on task scheduling, interrupt context, synchronization primitives, and driver architecture.) Company & Culture Questions:

• "What interests you about Snap Inc. and specifically this role in developing AR hardware?" (Connect your passion for hardware/software integration with Snap's mission in AR.)

• "How do you approach collaborating with engineers from different disciplines (e.g., RTL designers, verification engineers)?" (Highlight your communication skills and ability to understand different technical perspectives.)

• "Given Snap's 'default together' policy, how do you see yourself contributing to in-person team collaboration?" (Show enthusiasm for team activities and in-office synergy.)

• "How do you stay current with advancements in FPGA prototyping, emulation, and embedded systems?" (Demonstrate a commitment to continuous learning.) Portfolio Presentation Strategy:

• Executive Summary: Start with a high-level overview of your most impactful projects.

• Deep Dive on 1-2 Key Projects: For selected projects, walk through the problem, your solution, technical challenges, methodologies, and quantifiable results.

• Focus on "How": Emphasize your thought process, debugging techniques, and problem-solving strategies, not just the final outcome.

• Be Prepared for Code Review: Have key code snippets ready to explain specific implementation details.

• Quantify Impact: Whenever possible, use metrics (e.g., reduced debug time by X%, enabled Y% of software features pre-silicon).

• Engage Your Audience: Make it a conversation, inviting questions throughout or at specific points.

📝 Enhancement Note: Interview preparation should focus on demonstrating deep technical expertise in hardware-software integration, robust debugging skills, and a collaborative mindset. Be ready to articulate complex technical concepts clearly and concisely.

📌 Application Steps

To apply for this Prototyping Design Software Engineer position:

• Submit your application through the provided Workday link.

• Tailor your Resume: Highlight keywords and experiences directly related to SoC prototyping, FPGA/emulation (HAPS, ZeBu), embedded C/C++, RTOS, bare-metal development, and hardware-software debugging. Quantify achievements wherever possible.

• Prepare Your Portfolio: Curate examples of your work that showcase your skills in the areas mentioned above. Focus on projects involving platform bring-up, driver development, and complex debugging scenarios. Be ready to present this during an interview.

• Research Snap Inc. and Specs Inc.: Understand their products (Snapchat, Spectacles, Lens Studio), their mission, and their culture, particularly the "default together" policy and focus on AR.

• Practice Technical Questions: Review common embedded systems, RTOS, and hardware-software integration interview questions, and prepare to articulate your thought process and solutions clearly.

⚠️ Important Notice: This enhanced job description includes AI-generated insights and operations industry-standard assumptions. All details should be verified directly with the hiring organization before making application decisions.