Layout Principal Designer

📍 Job Overview

Job Title: Layout Principal Designer Company: SkyWater Technology Foundry, Inc. Location: Bloomington, Minnesota, United States Job Type: Full-time Category: Engineering / Semiconductor Design Date Posted: 2026-05-18T05:00:00 Experience Level: 5-10 years Remote Status: Hybrid (Remote OK)

🚀 Role Summary

• Lead critical custom layout and Electronic Design Automation (EDA) activities for semiconductor integrated circuit (IC) technologies, focusing on testchip collateral generation.
• Drive Process Design Kit (PDK) development for advanced CMOS and quantum technologies, contributing to modeling, reliability, and yield initiatives.
• Manage version control and library management for complex design projects involving multiple contributors, ensuring data integrity and efficient collaboration.
• Introduce and implement both custom and automated design methodologies to support diverse technology flows and derivative layout projects.
• Provide crucial feedback to internal teams on SkyWater PDK capabilities, identifying issues and suggesting improvements to enhance design efficiency and technology performance.

📝 Enhancement Note: This role is highly specialized within semiconductor design, requiring deep expertise in physical layout and EDA tools. While not a traditional "Revenue Operations" role, the focus on process development, efficiency, and contributing to product enablement aligns with the operational rigor expected in R&D and GTM support functions within technology companies. The emphasis on PDK development and testchip collateral directly supports the company's ability to bring new technologies to market, impacting revenue potential and market competitiveness.

📈 Primary Responsibilities

• Execute custom layout design for new structures essential for eTest, modeling, reliability, yield, and IP testchips, directly supporting new technology development lifecycles.
• Implement and manage version control systems for extensive design libraries, ensuring seamless collaboration and data integrity among multiple contributors.
• Design and integrate both custom and automated layout solutions for new and derivative projects, catering to a wide spectrum of technology flows and customer requirements.
• Actively utilize SkyWater PDKs, providing detailed feedback on encountered issues, potential improvements, and feature capabilities to internal development teams.
• Lead comprehensive physical verification processes, including Design Rule Checking (DRC), Electrical Rule Checking (ERC), Layout Versus Schematic (LVS), and Parasitic Extraction (PEX), ensuring design compliance and manufacturability.
• Oversee and manage tape-in reviews, coordinating with manufacturing and fabrication teams to ensure successful product integration and manufacturing readiness.
• Contribute to the development and optimization of Process Design Kits (PDKs) for advanced semiconductor technologies, including CMOS, MEMS, photonics, and superconducting.

📝 Enhancement Note: The responsibilities highlight a hands-on engineering role with significant ownership over the physical design process. The emphasis on PDK feedback and tape-in reviews signifies a crucial link between design and manufacturing, directly impacting yield and time-to-market. This role requires a strong understanding of the entire IC design flow from conception to tape-out.

🎓 Skills & Qualifications

Education:

• Master of Science (MS) in Electrical Engineering, Microelectronics, or a closely related field, OR equivalent practical experience.
• Bachelor of Science (BS) in Electrical Engineering, Microelectronics, or a related field with 5-7 years of relevant experience.

Experience:

• 7-10 years of progressive experience in Electronic Design fields, with a strong focus on physical layout and IC design methodologies.

Required Skills:

• Expert proficiency in custom layout design utilizing industry-standard IC EDA tool-assisted design flows, specifically including Cadence (e.g., Virtuoso) and Siemens EDA (e.g., Calibre) tool suites.
• Demonstrated familiarity and practical experience with layout automation techniques using scripting languages such as SKILL, Tcl, or Python.
• Solid knowledge and hands-on experience in developing and/or utilizing physical verification tools, including DRC, ERC, LVS/PEX, and DFM tooling.
• Proven experience in IP project management and/or managing complex design libraries with multiple contributors.
• Familiarity with typical mixed-signal IC design flows and considerations.
• Excellent communication skills, with the ability to provide clear, concise written reports and articulate technical concepts effectively.
• Inventive problem-solving capabilities with a proactive approach to identifying and resolving design challenges.
• Must be a U.S. Person (U.S. citizen, U.S. Permanent Resident, Political Asylee, or Refugee) due to ITAR compliance requirements.

Preferred Skills:

• Background in PDK development across one or more of the following areas: CMOS, MEMS, photonics, and superconducting technologies.
• Familiarity with advanced parasitic extraction tools, such as Mentor Calibre xRC, Cadence Quantus, or Synopsys StarRC.
• Experience managing IC design projects from architecture through GDSII generation, and fabrication from tape-out to post-silicon validation and testing.
• Experience with chemical-mechanical polishing (CMP) shape density filling techniques.
• Experience with data preparation and/or Optical Proximity Correction (OPC) methodologies.

📝 Enhancement Note: The requirement for U.S. Person status is a critical compliance factor for this role, directly impacting candidate eligibility due to ITAR regulations. The extensive list of required and preferred EDA tools and scripting languages emphasizes the technical depth expected for this Principal Designer position.

📊 Process & Systems Portfolio Requirements

Portfolio Essentials:

• Showcase a minimum of 2-3 complex IC layout projects, detailing the design challenges, methodologies employed, and final results.
• Include examples of custom layout structures designed for specific applications (e.g., test structures, IP blocks, critical analog/mixed-signal components).
• Demonstrate proficiency in using industry-standard EDA tools (Cadence, Siemens EDA, Calibre) through annotated screenshots or design files (where permissible).
• Highlight contributions to PDK development or library management, illustrating version control strategies and collaboration with multiple stakeholders.
• Provide evidence of automation scripting (SKILL, Tcl, Python) applied to layout tasks, including examples of scripts and their impact on efficiency or accuracy.

Process Documentation:

• Detail a specific process you followed for designing a complex layout block, from initial specification to tape-out readiness, including verification steps.
• Document your approach to managing design libraries with multiple contributors, emphasizing version control and conflict resolution strategies.
• Illustrate your methodology for providing feedback on PDKs, including how you identify, document, and communicate issues and improvement suggestions.
• Present a case study on how you used automation or scripting to solve a recurring layout problem or improve design flow efficiency.

📝 Enhancement Note: A strong portfolio is essential for this role, as it provides tangible proof of the required technical skills and experience. Candidates should be prepared to discuss their design choices, problem-solving approaches, and the impact of their work on project outcomes. The focus on process documentation aligns with the need for a systematic and efficient approach to layout design.

💵 Compensation & Benefits

Salary Range: $136,960 - $205,440 annually. This range is determined by factors including job-related experience, skills, education, and candidate qualifications. The specific pay offered will be based on a comprehensive evaluation.

Benefits:

• Financial Benefits:
  • Competitive salary and participation in incentive plans.
  • 401k matching program.
  • Life insurance coverage.
  • Opportunity to purchase SkyWater stock at a discounted rate.
• Health & Wellness:
  • Comprehensive benefits package effective from day one.
  • Medical, Dental, and Vision insurance plans.
  • Mental health benefits.
  • On-site fitness facility.
  • On-site self-serve market.
• Work-Life Balance:
  • Short-term and Long-term disability coverage.
  • Generous Paid Time Off (PTO).
  • Paid holidays.
• Additional Benefits:
  • Legal planning services.

Working Hours: Standard 40-hour work week, with potential for flexibility given the hybrid/remote option. Operations professionals in this role often benefit from flexible scheduling to accommodate complex design cycles and global collaboration, though core business hours will be expected for team interaction.

📝 Enhancement Note: The provided salary range is competitive for a Principal Designer role in the semiconductor industry, especially in the Minneapolis area. The comprehensive benefits package, including financial incentives and on-site amenities, reflects SkyWater's commitment to employee well-being and long-term engagement. The mention of remote work flexibility is a significant perk for operations and engineering roles.

🎯 Team & Company Context

🏢 Company Culture

Industry: Semiconductor Manufacturing (Foundry Services) Company Size: 251-500 employees (based on typical LinkedIn data for companies of this nature, though not explicitly provided). Founded: 2007 (SkyWater was established in 2007, evolving from a previous entity).

Team Structure:

• The Layout Principal Designer will likely be part of the Process Design Kit (PDK) development team or a dedicated IC Design Engineering group.
• This team typically operates with a hierarchical structure, with Principal Designers leading technical efforts and mentoring junior engineers.
• Cross-functional collaboration is essential, involving close interaction with process engineers, device physicists, modeling engineers, and potentially customer-facing technical teams.

Methodology:

• Data-Driven Design: Emphasis on using data from simulations, testchips, and fabrication runs to inform design decisions and PDK improvements.
• Process Optimization: Continuous effort to refine layout design rules, automation scripts, and verification flows to enhance efficiency, reduce errors, and improve manufacturing yield.
• Collaboration & Knowledge Sharing: A culture that encourages open communication, sharing of best practices, and collective problem-solving, especially within teams working on complex technologies.

Company Website: https://www.skywatertechnology.com/

📝 Enhancement Note: SkyWater positions itself as a leader in U.S.-based semiconductor manufacturing, focusing on advanced and emerging technologies. Their culture emphasizes innovation, integrity, and growth, which are crucial for a role involving cutting-edge PDK development. The company's commitment to "Bold Thinking. World Changing." suggests an environment where challenging projects and continuous learning are valued.

📈 Career & Growth Analysis

Operations Career Level: Principal Engineer / Senior IC Designer This role represents a senior-level position within the IC design and PDK development domain. It demands deep technical expertise, independent problem-solving, and the ability to guide complex projects. A Principal Designer is expected to be a subject matter expert, mentor junior engineers, and influence technical direction.

Reporting Structure: The Layout Principal Designer would likely report to an Engineering Manager or Director of Design Engineering, who oversees the PDK development or IC design teams. This structure provides a clear line of reporting while allowing for significant autonomy in day-to-day technical execution.

Operations Impact: This role has a direct impact on SkyWater's ability to successfully develop and commercialize new semiconductor technologies. By creating robust PDKs and high-quality testchip collateral, the Layout Principal Designer enables:

• Faster Time-to-Market: Efficient design enablement allows customers to bring their products to market quicker.
• Improved Yield & Reliability: Accurate layout rules and verification processes directly correlate to better manufacturing yield and device reliability.
• Technology Differentiation: Expertise in advanced technologies like quantum computing or novel device architectures helps SkyWater stand out in the competitive foundry market.
• Customer Enablement: Providing well-documented and functional PDKs is critical for customer adoption and success.

Growth Opportunities:

• Technical Specialization: Deepen expertise in specific advanced technologies (e.g., superconducting, photonics, quantum) or EDA tool development.
• Team Leadership: Transition into a formal management role (e.g., Engineering Manager) overseeing design teams or PDK development efforts.
• Architectural Design: Move into roles focused on high-level IC architecture or PDK strategy.
• Cross-Functional Roles: Contribute to GTM strategy by providing deep technical insights into product capabilities and customer needs, potentially bridging engineering and business development.
• Mentorship Programs: Formalize mentorship of junior engineers, developing leadership and coaching skills.

📝 Enhancement Note: The "Principal" title signifies a senior individual contributor path with significant technical influence. Growth opportunities are geared towards deepening technical mastery, leading teams, or influencing strategic direction within the company's advanced technology initiatives.

🌐 Work Environment

Office Type: Hybrid - primarily based in Bloomington, MN, with remote work flexibility. This suggests a modern office environment designed for collaboration, potentially with dedicated design labs and shared workspaces. Office Location(s): Bloomington, Minnesota (HQ). The company also has locations in Florida and Texas, though this specific role is based in MN.

Workspace Context:

• Collaborative Spaces: The office environment likely includes meeting rooms, open work areas, and potentially quiet zones to support focused design work and team collaboration.
• Advanced Tools & Technology: Access to high-performance computing resources, specialized EDA software licenses, and robust network infrastructure is expected for IC design work.
• Team Interaction: Opportunities for regular interaction with fellow layout engineers, PDK developers, process engineers, and management through team meetings, design reviews, and informal discussions.

Work Schedule: Standard 40-hour work week is expected, with potential for flexibility. Given the nature of semiconductor design and potential for urgent tape-outs or issue resolution, occasional extended hours or weekend work might be necessary, though this is generally managed through project planning and team support.

📝 Enhancement Note: The hybrid model indicates a balance between in-office collaboration and remote flexibility, appealing to professionals who value both focused work and work-life integration. The Bloomington HQ likely offers modern facilities to support the demanding nature of semiconductor design.

📄 Application & Portfolio Review Process

Interview Process:

1. Initial Screening: HR or recruiter call to assess basic qualifications, interest, and fit with company culture.
2. Technical Interview 1 (EDA & Layout Focus): In-depth discussion on custom layout design experience, proficiency with specific EDA tools (Cadence, Siemens EDA, Calibre), and scripting capabilities (SKILL, Python). Expect scenario-based questions related to layout challenges.
3. Technical Interview 2 (PDK & Verification Focus): Focus on PDK development experience, understanding of physical verification (DRC, LVS, LPE), mixed-signal design considerations, and problem-solving methodologies. May include a discussion of past projects and contributions.
4. Portfolio Review Session: A dedicated session where the candidate presents selected projects from their portfolio. This is a critical step to demonstrate practical skills, design thinking, and communication ability. Expect detailed questions about design choices, challenges overcome, and results achieved.
5. Hiring Manager Interview: Discussion on leadership potential, team fit, career aspirations, and alignment with SkyWater's values. May involve broader strategic questions related to semiconductor technology trends.
6. Final Interview/Offer: Potential final discussion with senior leadership, followed by an offer.

Portfolio Review Tips:

• Curate Selectively: Choose 3-5 of your strongest, most relevant projects that showcase your expertise in custom layout, automation, and PDK contributions.
• Quantify Impact: For each project, clearly articulate the problem, your solution, the tools used, and the quantifiable results (e.g., reduced design time by X%, improved verification coverage, enabled specific technology feature).
• Highlight Process: Explain your design methodology, verification steps, and how you collaborated with others.
• Be Prepared for Deep Dives: Anticipate detailed technical questions about your design choices, EDA tool configurations, and problem-solving approaches.
• Address Security: Be mindful of any proprietary information; sanitize designs or use representative examples if necessary.

Challenge Preparation:

• Scripting Challenge: You might be asked to write or debug a simple SKILL, Tcl, or Python script for a common layout task (e.g., parameterization, data extraction).
• Layout Problem-Solving: Be ready to discuss how you would approach a hypothetical complex layout scenario or a verification failure.
• PDK Feedback Scenario: Prepare to describe how you would document and communicate an issue found in a PDK.

📝 Enhancement Note: The interview process emphasizes both deep technical skills and the ability to articulate them effectively, particularly through the portfolio review. Candidates should prepare specific examples that demonstrate their problem-solving abilities and contributions to efficient design flows and robust PDKs.

🛠 Tools & Technology Stack

Primary Tools:

• Custom Layout Design: Cadence Virtuoso, Siemens EDA (e.g., Pyxis, Custom Compiler).
• Physical Verification: Mentor Graphics Calibre (DRC, LVS, PEX), Siemens EDA (e.g., PVS), Synopsys IC Validator.
• Scripting & Automation: SKILL (Cadence), Tcl, Python.
• Parasitic Extraction: Mentor Calibre xRC, Cadence Quantus, Synopsys StarRC.
• DFM Tools: Various tools from Siemens EDA, Mentor Graphics, or Synopsys for Design for Manufacturability.

Analytics & Reporting:

• While not directly managing business analytics, the role involves analyzing simulation results, verification reports, and design metrics to assess layout quality and efficiency. Tools may include internal scripts, data analysis platforms, or standard office productivity suites.

CRM & Automation:

• Not directly applicable to this role, as it is focused on the engineering design process rather than sales or customer management.

📝 Enhancement Note: Expertise in the specified EDA tools and scripting languages is non-negotiable. Familiarity with the broader semiconductor design toolchain, including verification and extraction tools, is highly advantageous. Candidates should be prepared to discuss their experience and proficiency with these specific technologies.

👥 Team Culture & Values

Operations Values:

• Integrity: Upholding ethical standards in design, data handling, and communication. This is paramount in semiconductor design where precision and honesty are critical.
• Excellence: Striving for the highest quality in layout design, verification, and PDK development, ensuring robust and reliable semiconductor technologies.
• Collaboration: Working effectively with cross-functional teams (process engineering, modeling, etc.) to achieve shared goals, fostering an environment of mutual respect and shared success.
• Empowerment: Taking ownership of design tasks, proactively identifying solutions, and contributing innovative ideas to drive technological advancements.
• Growth Mindset: Continuously learning new technologies, tools, and methodologies in the fast-evolving semiconductor industry, and sharing this knowledge with the team.

Collaboration Style:

• Cross-Functional Integration: Regular engagement with process engineers to understand technology constraints and with modeling engineers to ensure layout accurately reflects device behavior.
• Process Review & Feedback: A culture of constructive feedback during design reviews and PDK check-ins, aimed at improving designs and processes collectively.
• Knowledge Sharing: Encouraging team members to share best practices, new techniques, and solutions to common layout challenges through internal documentation, presentations, or informal discussions.

📝 Enhancement Note: SkyWater's stated values are directly applicable to the engineering team. The emphasis on collaboration and a growth mindset is particularly important for a role involved in developing cutting-edge technologies where continuous learning and teamwork are essential for success.

⚡ Challenges & Growth Opportunities

Challenges:

• Complexity of Advanced Technologies: Working with novel device topologies (e.g., quantum, superconducting) presents unique layout challenges that may not have established solutions, requiring innovative approaches.
• PDK Development & Maintenance: Keeping PDKs accurate, up-to-date with evolving process technologies, and user-friendly for diverse customer needs is an ongoing challenge.
• Balancing Custom vs. Automated Design: Effectively integrating custom layout solutions with automated flows to maximize efficiency without sacrificing critical design requirements.
• ITAR Compliance: Ensuring all design activities and documentation adhere strictly to ITAR regulations, which can add complexity to project management and collaboration.

Learning & Development Opportunities:

• Advanced Technology Exposure: Gaining hands-on experience with emerging semiconductor technologies that are shaping the future of electronics.
• EDA Tool Mastery: Deepening expertise in leading EDA tools and potentially contributing to their development or customization through scripting.
• Process Technology Understanding: Developing a comprehensive understanding of semiconductor fabrication processes and their impact on layout design.
• Mentorship & Leadership: Opportunities to mentor junior engineers and take on project leadership roles, fostering career growth towards senior technical or management positions.

📝 Enhancement Note: The challenges presented are inherent to working in a leading-edge semiconductor foundry. Growth opportunities are substantial, offering a path for deep technical specialization and leadership within a critical industry.

💡 Interview Preparation

Strategy Questions:

• "Describe a complex custom layout challenge you faced and how you successfully resolved it. What was the impact?" (Focus on problem-solving, technical depth, and result quantification.)
• "How do you approach building and managing a large design library with multiple contributors? What version control strategies do you employ?" (Assess organizational skills, collaboration, and data management.)
• "Walk me through your process for providing feedback on a PDK. What criteria do you use, and how do you communicate your findings effectively?" (Evaluate communication, critical analysis, and process improvement mindset.)
• "Describe your experience with layout automation. Provide an example of a script you wrote and the benefit it provided." (Demonstrate scripting proficiency and efficiency focus.)

Company & Culture Questions:

• "What interests you about SkyWater's focus on U.S.-based semiconductor manufacturing and its advanced technologies (e.g., quantum, superconducting)?" (Showcase research and genuine interest.)
• "How do you embody SkyWater's values of Integrity, Excellence, Collaboration, Empowerment, and Growth Mindset in your work?" (Prepare specific examples.)
• "How do you stay current with the latest trends and tools in semiconductor layout design and EDA?" (Highlight continuous learning and proactive development.)

Portfolio Presentation Strategy:

• Structure: For each portfolio piece, use a clear structure: Problem -> Your Solution -> Tools & Methodology -> Results/Impact.
• Visuals: Use clear, annotated screenshots of layouts, verification reports, and automation scripts. Highlight key areas and explain their significance.
• Storytelling: Frame your projects as stories of problem-solving and innovation. Explain the "why" behind your design choices.
• Quantify: Wherever possible, use numbers and metrics to demonstrate the impact of your work (e.g., time savings, error reduction, yield improvement).
• Engagement: Be ready to pause and answer questions throughout your presentation, fostering an interactive discussion rather than a one-way monologue.

📝 Enhancement Note: Preparation should focus on articulating technical expertise through concrete examples and demonstrating alignment with SkyWater's values and mission. The portfolio review is a key differentiator, so thorough preparation here is crucial.

📌 Application Steps

To apply for this Layout Principal Designer position:

• Submit your application through the provided link on the Dayforce portal.
• Tailor your resume: Highlight specific keywords from the job description, emphasizing your expertise in Cadence Virtuoso, Siemens EDA tools, Calibre, and scripting languages like Python or SKILL. Quantify your years of experience and achievements.
• Prepare your portfolio: Curate 3-5 of your most impactful IC layout projects. Ensure they showcase custom design, automation, verification, and ideally, contributions to PDK development. Be ready to present and discuss them in detail.
• Research SkyWater Technology: Understand their mission, technologies (CMOS, quantum, etc.), company values, and recent news. This will help you articulate your interest and align your responses during interviews.
• Practice your interview responses: Prepare for technical questions about layout design, EDA tools, verification, and scripting. Rehearse your portfolio presentation and be ready to discuss your problem-solving approach and collaboration style.

⚠️ Important Notice: This enhanced job description includes AI-generated insights and industry-standard assumptions. All details should be verified directly with SkyWater Technology Foundry, Inc. before making application decisions. Particular attention should be paid to the U.S. Person requirement for ITAR compliance.