Digital Design Manager

📍 Job Overview

Job Title: ASIC Digital Design Manager

Company: OLIX

Location: Austin, Texas, United States

Job Type: FULL_TIME

Category: Engineering Management / ASIC Design

Date Posted: 2026-05-01

Experience Level: 10+ Years

🚀 Role Summary

• Lead end-to-end delivery of complex digital subsystems for next-generation high-speed mixed-signal ASICs, focusing on aggressive schedule targets and first-time-right silicon.

• Manage, mentor, and grow a high-performing team of 6-12 digital ASIC engineers, overseeing goal-setting, performance reviews, and career development.

• Drive seamless cross-functional collaboration across analog, verification, layout, packaging, firmware, and test teams to ensure program alignment and execution speed.

• Provide technical direction and architectural guidance for high-speed digital subsystems, including multi-lane data paths, clocking, and advanced mixed-signal control loops.

• Champion a culture of speed and quality through design automation, streamlined methodologies, and knowledge sharing to achieve high-quality silicon on tight timelines.

📝 Enhancement Note: While the title is "Digital Design Manager," the core responsibilities and required skills heavily emphasize ASIC (Application-Specific Integrated Circuit) development and management within a semiconductor context, aligning it with specialized hardware engineering leadership rather than general digital design. The role requires a strong understanding of the full ASIC lifecycle from specification through production.

📈 Primary Responsibilities

• Execution Ownership & Speed: Take full ownership of the end-to-end delivery of digital subsystems, including RTL design, synthesis, DFT/DFD, timing closure, and physical implementation, ensuring aggressive schedule targets are consistently met without compromising quality.

• Right-First-Time Delivery: Establish and enforce robust design, verification, and silicon bring-up processes that prioritize first-silicon success and minimize costly re-spins.

• Performance Management: Lead, mentor, and develop a team of 6-12 digital engineers. This includes setting clear goals, conducting performance reviews, fostering career growth, and actively participating in hiring to build a high-performing, accountable team.

• Cross-Functional Alignment: Ensure seamless integration and communication with analog design, verification, layout, packaging, firmware, and test teams, facilitating rapid and aligned program execution from architecture specification to tape-out and bring-up.

• Program Leadership: Define, track, and manage aggressive schedules, resource allocation, and risk mitigation strategies. Provide clear, concise communication of progress, trade-offs, and escalation paths to executive leadership and external customers.

• Technical Direction: Offer expert architectural and implementation guidance for complex high-speed digital subsystems, such as multi-lane high-bandwidth data paths, intricate clocking schemes, and sophisticated mixed-signal control loops.

• Culture of Speed & Quality: Actively promote and implement design automation tools, streamlined methodologies, and effective knowledge-sharing practices to accelerate the delivery of high-quality silicon within demanding timelines.

📝 Enhancement Note: The responsibilities highlight a blend of technical leadership and people management, crucial for an ASIC Design Manager. The emphasis on "Execution Ownership & Speed" and "Right-First-Time Delivery" indicates a high-pressure, results-oriented environment common in semiconductor development. The cross-functional alignment responsibility is critical given the complex interplay between digital, analog, and physical design aspects in ASIC development.

🎓 Skills & Qualifications

Education: While not explicitly stated, a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field is typically expected for ASIC design roles. Advanced degrees are often preferred for leadership positions.

Experience:

• A minimum of 10 years of hands-on experience in digital ASIC development.

• At least 3 full product cycles successfully executed from initial specification to high-volume production.

Required Skills:

• RTL Design: Strong expertise in RTL design using SystemVerilog and/or Verilog.

• Verification & Timing: Proficiency in Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Static Timing Analysis (STA), and synthesis.

• Physical Design & Power: Experience with Place & Route (P&R), power intent methodologies (UPF/CPF), and Design for Test/Design for Debug (DFT/DFD).

• Mixed-Signal Interaction: Deep understanding of mixed-signal design challenges, including coupling, jitter, supply noise, and calibration, with the ability to effectively collaborate with analog teams on specification splits.

• Leadership & Management: Demonstrated success in line management, including hiring, mentoring, performance management, and developing high-performing engineering teams.

• Program Management: Skilled in fast-paced, cross-functional program leadership, with a proven ability to manage schedules, identify and mitigate risks, and manage vendor/foundry relationships.

• Communication: Outstanding written and verbal communication skills, with confidence in presenting clear, concise program and technical status to executives, customers, and distributed teams.

Preferred Skills:

• Experience with specific high-speed interfaces such as SerDes.

• Familiarity with mixed-signal interface types like DACs/ADCs, RF SoCs, or display/camera pipelines.

• Experience with silicon bring-up and post-silicon validation.

• Knowledge of advanced packaging technologies and their impact on digital design.

📝 Enhancement Note: The "Skills & Experience" section is highly technical and specific to the semiconductor industry. The requirement for "3 full product cycles successfully executed from specification to high-volume production" is a critical indicator of the practical, end-to-end experience expected. The emphasis on mixed-signal interaction and the ability to partner with analog teams is a key differentiator for this role.

📊 Process & Systems Portfolio Requirements

Portfolio Essentials:

• ASIC Design Process Documentation: Showcase examples of documented ASIC design flows, including RTL development, synthesis, timing closure, and physical implementation stages.

• First-Time-Right Success Cases: Present case studies or project summaries highlighting methodologies and outcomes that led to successful first-silicon tape-outs and minimal post-silicon issues.

• Mixed-Signal Integration Examples: Include examples of how digital subsystems were designed to effectively integrate with and mitigate potential interference from mixed-signal components.

• Team Management & Process Improvement: Provide evidence of implementing team processes, performance tracking, and initiatives that improved team efficiency, quality, or delivery speed.

Process Documentation:

• Workflow Design & Optimization: Demonstrate the ability to design, document, and optimize complex ASIC development workflows, from initial architecture to final tape-out and production.

• Methodology Implementation: Showcase experience in implementing and refining design methodologies, including RTL coding standards, verification strategies, DFT insertion, and timing closure flows.

• Performance Measurement & Analysis: Illustrate how you have defined and tracked key performance indicators (KPIs) for digital design teams and projects, using data to drive improvements and report on progress.

📝 Enhancement Note: For an ASIC Digital Design Manager, a portfolio is not just about individual contributions but about demonstrating leadership in managing the entire ASIC development lifecycle. The focus should be on process, team execution, and achieving tangible results like first-time-right silicon and on-time delivery. Demonstrating an understanding of the end-to-end flow and the ability to manage complex interdependencies is crucial.

💵 Compensation & Benefits

Salary Range: $388,000+ annually, commensurate with experience, skills, and location.

• 📝 Enhancement Note: The provided salary is a base figure and the note indicates it's a starting point, suggesting potential for higher compensation based on the candidate's profile and negotiation. The $36k annual "Living-Local Bonus" for employees residing within 20 minutes of the office is a unique perk that significantly impacts total compensation for local hires.

Benefits:

• Equity & Ownership: Meaningful stock options are offered, providing employees with ownership in the company's mission and success.

• Living-Local Bonus: A $36,000 annual bonus for employees living within a 20-minute commute of the office, aimed at valuing employee time and reducing commute burdens.

• Time Off: A generous 33 days of paid time off (PTO), including US federal holidays.

• Healthcare Coverage: Multiple high-quality medical plan options, including comprehensive family coverage.

• Health Savings Account (HSA): Available with a high-deductible medical option, supplemented by a company-funded HSA.

• Dental & Vision: Full dental and vision coverage.

• Additional Coverage: Life insurance, as well as short- and long-term disability insurance.

• Wellbeing Support: Access to mental health resources, and support for fertility and family-building initiatives.

• Commuter Benefits: Pre-tax commuter and parking benefits to ease daily travel.

• Retirement Plan: 401(k) retirement plan with a 4% employer match, offering both traditional and Roth contribution options.

• Financial Advisory: Access to a dedicated financial advisor for portfolio selection and long-term planning support.

• Visa Sponsorship: Full UK and international visa sponsorship is available for eligible candidates.

• Relocation Support: Dedicated relocation partner providing funding and concierge services for seamless domestic and international moves.

Working Hours: Standard 40 hours per week, with the understanding that occasional late work may be required, especially with chef-prepared meals available if working late.

📝 Enhancement Note: OLIX offers a highly competitive and comprehensive benefits package, particularly noteworthy for the significant "Living-Local Bonus" and extensive stock options. The inclusion of visa sponsorship and robust relocation support highlights the company's commitment to attracting global talent.

🎯 Team & Company Context

🏢 Company Culture

Industry: Semiconductor / AI Infrastructure. OLIX is positioned at the forefront of AI infrastructure, addressing the critical hardware limitations hindering AI's exponential growth. The company is developing novel ASIC accelerators (DX-1) that represent a new paradigm in speed and efficiency, aiming to be a major economic and technological force.

Company Size: The description implies a growth-stage company, likely a startup or scale-up, given the focus on innovation, aggressive schedules, and the "meaningful stock options" benefit. The engineering team size for digital engineers is 6-12, suggesting a focused, agile team structure.

Founded: OLIX is a relatively new entity, established to address the limitations of current AI hardware by developing a new architectural paradigm. The company is driven by the rapid advancement of AI technology and the resulting infrastructure gap.

Team Structure:

• Digital ASIC Team: A core team of 6-12 digital engineers responsible for RTL design, synthesis, timing, DFT, and physical implementation.

• Cross-Functional Collaboration: The role requires deep integration with analog design, verification, layout, packaging, firmware, and test teams, indicating a highly collaborative, matrixed project environment.

• Reporting: While not explicitly stated, the Manager role likely reports to a Director or VP of Engineering, with direct reports being the digital ASIC engineers.

Methodology:

• Execution Speed & Quality: A dual focus on delivering complex ASICs rapidly while ensuring first-time-right silicon success.

• Data-Driven Decision Making: Implied through the need for rigorous verification, STA, and performance analysis.

• Agile Development Practices: The emphasis on aggressive schedules and rapid iteration suggests an agile or iterative approach to ASIC development.

• Co-Design Philosophy: The company's description highlights a "rack-scale co-design" approach for logic, data movement, packaging, optics, and interconnect, indicating a holistic design philosophy.

Company Website: https://www.olix.com

📝 Enhancement Note: OLIX is operating in a highly innovative and competitive space, focusing on solving fundamental infrastructure challenges for AI. The company culture is likely fast-paced, demanding, and focused on technical excellence and rapid execution, appealing to engineers who thrive in cutting-edge environments. The emphasis on co-design suggests a strong interdisciplinary approach.

📈 Career & Growth Analysis

Operations Career Level: This role is a senior management position within the ASIC Digital Design discipline. It sits at the intersection of deep technical expertise in ASIC development and people/program leadership. The scope includes direct management of engineers, ownership of critical ASIC subsystems, and significant influence on project timelines and success.

Reporting Structure: The Digital Design Manager will likely report to a Director or VP of Engineering. They will manage a team of 6-12 digital ASIC engineers, and will be responsible for coordinating closely with leads and engineers from other disciplines (analog, verification, layout, firmware, test).

Operations Impact: The impact of this role is profound. Successful execution of digital subsystems directly dictates the performance, efficiency, and time-to-market of OLIX's groundbreaking AI accelerators. This role is instrumental in translating architectural vision into tangible silicon, directly influencing the company's ability to capture market share and fulfill its mission in the rapidly evolving AI infrastructure landscape.

Growth Opportunities:

• Technical Specialization: Deepen expertise in high-speed digital design, advanced mixed-signal integration, and novel AI hardware architectures.

• Leadership Advancement: Progress to higher management roles such as Director or VP of Engineering, overseeing larger teams and broader engineering functions.

• Strategic Contribution: Influence architectural decisions, technology roadmaps, and long-term product strategy for OLIX's AI accelerator roadmap.

• Cross-Disciplinary Mastery: Gain comprehensive understanding and influence across the entire ASIC development flow, from architecture to production.

• Industry Recognition: Contribute to pioneering work in AI hardware that could lead to industry-wide impact and personal recognition.

📝 Enhancement Note: This is a pivotal role for an ambitious engineering leader. The growth path is clear for those who excel in both technical execution and team leadership, offering opportunities to shape the future of AI hardware at a company poised for significant impact. The role offers a unique chance to be at the forefront of a technological revolution.

🌐 Work Environment

Office Type: On-site, with a strong emphasis on collaboration and focus. The company provides high-spec equipment and an environment designed for deep work.

Office Location(s): Austin, Texas, United States. This location is a hub for technology and semiconductor talent.

Workspace Context:

• High-Performance Technology: Standard equipment includes M4 Macs, with M4 Pro upgrades for the engineering team, ensuring engineers have top-tier tools.

• Focused Environment: High-spec noise-cancelling headphones and fully ergonomic workstations are provided to facilitate deep concentration and productivity.

• Collaborative Spaces: While the focus is on individual deep work, the on-site nature and cross-functional collaboration requirements imply available meeting rooms and common areas for interaction.

• On-site Amenities: Chef-prepared meals are available for those working late, indicating a supportive environment that prioritizes employee well-being and productivity.

• Prototyping Access: Access to a high-performance 3D printing lab for work, experimentation, and personal projects, fostering innovation and rapid iteration.

Work Schedule: A standard 40-hour work week is indicated, but the nature of ASIC development and the company's emphasis on speed suggests that flexibility and dedication, potentially including occasional extended hours, will be necessary to meet aggressive project timelines.

📝 Enhancement Note: OLIX provides a premium on-site work environment tailored for high-performance engineering. The investment in top-tier technology, ergonomic setups, and amenities like catered meals underscores a commitment to enabling engineers to do their best work in a focused, collaborative, and supportive setting. The "Living-Local Bonus" further incentivizes on-site presence.

📄 Application & Portfolio Review Process

Interview Process:

• Initial Screening: Review of resume and application to assess alignment with technical requirements and leadership experience. Emphasis on ASIC development lifecycle experience and team management.

• Technical Deep Dive: Interviews focusing on ASIC design methodologies, RTL coding, STA, synthesis, DFT, and mixed-signal integration. Candidates will be expected to discuss past projects in detail.

• Engineering Management Assessment: Interviews assessing leadership style, team building, performance management, problem-solving, and cross-functional collaboration skills.

• Cross-Functional Interviews: Meetings with leads or members from other engineering teams (analog, verification, firmware) to evaluate collaboration capabilities and understanding of interdependencies.

• Executive/VP Interview: A final discussion, potentially with the VP of Engineering or CTO, to assess strategic thinking, cultural fit, and overall alignment with OLIX's mission and pace.

Portfolio Review Tips:

• ASIC Lifecycle Focus: Present projects that clearly demonstrate your involvement across multiple stages of the ASIC lifecycle (specification, design, verification handoff, timing closure, P&R considerations, DFT insertion, tape-out, and ideally, silicon bring-up).

• Quantifiable Achievements: For each project, highlight specific achievements related to schedule adherence, first-time-right silicon success, performance improvements, power optimization, or team efficiency gains. Use metrics where possible.

• Leadership Examples: Showcase how you managed teams, mentored engineers, resolved conflicts, and fostered a collaborative environment. Include examples of process improvements you implemented.

• Technical Depth & Breadth: Be prepared to discuss complex technical challenges encountered and how you and your team overcame them. Demonstrate a strong understanding of the interplay between digital, analog, and physical design.

• Concise & Clear: Present your portfolio in a structured, easy-to-understand manner. Focus on impact and outcomes rather than just listing tasks.

Challenge Preparation:

• Scenario-Based Questions: Expect questions that present hypothetical ASIC development challenges (e.g., a critical timing violation discovered late in the flow, unexpected analog noise impacting digital performance, a missed schedule milestone). Be prepared to outline your approach to diagnosing and resolving these issues, emphasizing collaboration and process.

• Team Management Scenarios: Prepare for questions about handling underperforming team members, managing conflict within the team, motivating engineers, and implementing new development processes.

• Strategic Thinking: Consider how you would prioritize competing demands, manage risks for a critical project, and contribute to the overall ASIC technology roadmap.

📝 Enhancement Note: The interview process will be rigorous, testing both deep technical ASIC expertise and strong leadership capabilities. A well-curated portfolio that showcases end-to-end ASIC lifecycle management and demonstrable leadership impact will be crucial for success. Candidates should be ready to discuss their management philosophy and how they drive both technical excellence and team performance.

🛠 Tools & Technology Stack

Primary Tools:

• RTL Design: SystemVerilog, Verilog.

• Simulation & Verification: EDA tools for simulation, formal verification, and static analysis (e.g., Synopsys VCS, Cadence Xcelium, Mentor Graphics QuestaSim).

• Synthesis: Logic synthesis tools (e.g., Synopsys Design Compiler, Cadence Genus).

• Timing Analysis: Static timing analysis tools (e.g., Synopsys PrimeTime, Cadence Tempus).

• Physical Implementation: Place & Route (P&R) tools (e.g., Synopsys IC Compiler II, Cadence Innovus).

• DFT/DFD: Tools for Design for Test and Design for Debug insertion and analysis.

• Power Analysis: Tools for UPF/CPF analysis and power intent implementation.

Analytics & Reporting:

• Project Management Software: Tools for tracking schedules, resources, and risks (e.g., Jira, Asana, Microsoft Project).

• Collaboration Platforms: Tools for team communication and knowledge sharing (e.g., Slack, Microsoft Teams).

• Reporting Tools: Standard office suites for generating reports and presentations.

CRM & Automation:

• While not directly related to ASIC design, the company likely uses CRM for business operations. Understanding how engineering output aligns with business goals is beneficial.

• EDA Tool Scripting: Proficiency in scripting languages like Tcl, Python, or Perl is often required for automating EDA tool flows and custom checks.

📝 Enhancement Note: The technology stack is heavily focused on industry-standard Electronic Design Automation (EDA) tools used in semiconductor development. Proficiency in the core RTL design, synthesis, timing, and physical implementation tools is a baseline requirement. Automation skills, particularly with scripting languages, are highly valued for improving efficiency in complex design flows.

👥 Team Culture & Values

Operations Values:

• Speed & Execution: A paramount value, emphasizing rapid iteration, quick decision-making, and aggressive delivery timelines.

• Quality & Precision: A commitment to "first-time-right" silicon, demanding rigorous design, verification, and testing to ensure uncompromising quality.

• Collaboration & Alignment: Fostering strong partnerships across diverse engineering disciplines to achieve common goals efficiently.

• Accountability & Ownership: Encouraging individuals and teams to take full responsibility for their work and its outcomes.

• Innovation & Problem-Solving: A culture that embraces tackling complex technical challenges and developing novel solutions for the AI infrastructure gap.

Collaboration Style:

• Interdisciplinary Integration: Expect a highly collaborative environment where digital, analog, verification, layout, firmware, and test engineers work in close concert, sharing information and resolving dependencies proactively.

• Open Communication: A culture that values clear, concise, and timely communication, especially when escalating issues or discussing trade-offs.

• Process-Oriented: While fast-paced, there's an emphasis on well-defined processes to ensure quality and repeatability, with a willingness to refine methodologies for greater efficiency.

• Knowledge Sharing: Encouragement of sharing best practices, lessons learned, and technical insights across teams to accelerate learning and prevent recurring issues.

📝 Enhancement Note: OLIX's culture appears to be a blend of high-octane startup energy with the meticulous discipline required for semiconductor development. The ideal candidate will be driven by a desire to innovate and deliver rapidly, while also prioritizing technical accuracy and collaborative problem-solving.

⚡ Challenges & Growth Opportunities

Challenges:

• Aggressive Timelines: Meeting demanding schedules for complex ASIC development in a rapidly evolving AI market.

• First-Time-Right Silicon: The inherent difficulty and risk associated with achieving perfect silicon on the first attempt, requiring meticulous design and verification.

• Cross-Functional Dependencies: Effectively managing and aligning diverse engineering teams with potentially competing priorities and different development cycles.

• Rapid Technological Evolution: Staying abreast of advancements in AI hardware, semiconductor technology, and design methodologies.

• Scaling the Team: Growing and managing a high-performing engineering team while maintaining culture and quality standards.

Learning & Development Opportunities:

• Cutting-Edge Technology: Gaining deep experience with novel AI accelerator architectures and advanced semiconductor fabrication processes.

• Leadership Development: Enhancing people management, strategic planning, and cross-functional leadership skills within a high-growth environment.

• Industry Impact: Contributing to a product that aims to redefine AI infrastructure and has the potential for significant market disruption.

• Technical Mastery: Deepening expertise in all facets of ASIC design, from advanced RTL to silicon bring-up and production.

• Mentorship: Opportunities to mentor junior engineers and learn from experienced leaders within OLIX.

📝 Enhancement Note: The challenges presented are inherent to leading advanced hardware development in a cutting-edge field. Success hinges on effective risk management, strong technical acumen, and exceptional leadership. The growth opportunities are substantial for those who thrive in dynamic, high-impact environments.

💡 Interview Preparation

Strategy Questions:

• ASIC Development Lifecycle: "Describe your approach to managing the entire ASIC development lifecycle from specification to tape-out and production. What are the key milestones and potential pitfalls at each stage?" (Focus on process, risk mitigation, and cross-functional handoffs.)

• Team Performance & Scaling: "How would you build and motivate a high-performing ASIC design team of 6-12 engineers? What strategies would you employ to scale the team while maintaining quality and speed?" (Highlight people management, goal setting, and process improvement.)

• Mixed-Signal Collaboration: "Imagine a scenario where analog team reports significant noise coupling impacting your digital subsystem. How would you collaborate with them to diagnose, spec, and resolve this issue?" (Emphasize communication, technical understanding, and problem-solving.)

Company & Culture Questions:

• Pace & Culture: "OLIX emphasizes speed and quality. How do you balance these two often competing priorities in a fast-paced engineering environment?" (Showcase an understanding of their values and how you've managed this balance.)

• Leadership Philosophy: "What is your philosophy on leading engineering teams, particularly in a startup or high-growth environment focused on innovation?" (Discuss mentorship, accountability, and fostering a positive, productive culture.)

• Impact & Vision: "How do you see this role contributing to OLIX's mission of addressing the AI infrastructure gap, and what impact do you aim to make in your first year?" (Align your experience with the company's strategic goals.)

Portfolio Presentation Strategy:

• STAR Method: Structure your project examples using the Situation, Task, Action, Result (STAR) method to clearly articulate your contributions and their impact.

• Quantify Everything: Whenever possible, use numbers and metrics (e.g., "reduced timing violations by X%", "achieved Y% schedule improvement," "delivered Z% first-time-right silicon").

• Focus on Leadership: For management roles, highlight instances where you led teams, mentored individuals, improved processes, or resolved complex team/project issues.

• Visual Aids: Use clear diagrams, flowcharts, or simplified schematics to illustrate complex technical concepts or workflows if presenting digitally.

• Concise Storytelling: Be prepared to walk through your most impactful projects concisely, focusing on the key challenges, your strategic approach, and the tangible outcomes.

📝 Enhancement Note: Preparation should focus on demonstrating a blend of deep technical ASIC knowledge and effective leadership. Candidates should be ready to discuss their management style, problem-solving approaches, and how they drive teams to achieve ambitious goals in a demanding environment.

📌 Application Steps

To apply for this ASIC Digital Design Manager position:

• Submit your application through the provided link on Ashby.

• Portfolio Customization: Tailor your resume and any supplementary materials to highlight your experience in full ASIC lifecycle management, team leadership, and successful silicon delivery. Emphasize your experience with RTL design, synthesis, timing closure, DFT, and mixed-signal interactions.

• Resume Optimization: Ensure your resume clearly articulates your 10+ years of ASIC development experience, specifically mentioning at least 3 full product cycles from specification to high-volume production. Quantify achievements where possible.

• Interview Preparation: Practice discussing your most significant ASIC projects, focusing on your role as a leader and manager. Be ready to articulate your approach to team building, performance management, and cross-functional collaboration.

• Company Research: Thoroughly research OLIX's mission, technology, and the current landscape of AI infrastructure. Understand their focus on speed, quality, and co-design. Prepare thoughtful questions about their technology roadmap, team structure, and engineering culture.

⚠️ Important Notice: This enhanced job description includes AI-generated insights and operations industry-standard assumptions. All details should be verified directly with OLIX before making application decisions.