Digital Design Manager

📍 Job Overview

Job Title: ASIC Digital Design Manager

Company: OLIX

Location: Bristol, England, United Kingdom

Job Type: FULL_TIME

Category: Engineering / Technology / Management & Leadership

Date Posted: 2026-05-01

Experience Level: 10+ years

Remote Status: On-site

🚀 Role Summary

• Lead end-to-end digital subsystem delivery for high-speed mixed-signal ASICs, focusing on aggressive schedule adherence and first-time-right silicon success.

• Manage, mentor, and develop a team of 6-12 digital engineers, fostering a culture of accountability and continuous improvement.

• Drive seamless cross-functional collaboration between digital, analog, verification, layout, packaging, firmware, and test teams to accelerate program execution.

• Provide technical direction and architectural guidance for complex digital systems, including high-bandwidth interfaces and deterministic control loops.

📝 Enhancement Note: This role is positioned as a critical leadership function within OLIX's ASIC development lifecycle. The emphasis on "execution speed," "first-time-right delivery," and "cross-functional alignment" strongly indicates a need for a candidate with proven project management capabilities and a deep understanding of the entire ASIC development flow, from concept to mass production. The "Digital Design Manager" title, coupled with the responsibilities, suggests a hybrid role that blends technical authority with people management, requiring a strategic approach to resource allocation and risk mitigation.

📈 Primary Responsibilities

• Oversee the complete lifecycle of digital subsystems, including RTL design, synthesis, Design for Test (DFT)/Design for Debug (DFD), timing closure, and physical implementation, ensuring aggressive schedule targets are met without compromising quality.

• Establish and enforce robust design and verification processes to achieve first-silicon success, integrating silicon bring-up strategies from the outset.

• Manage individual performance, goal setting, career development, and hiring for a team of 6-12 digital engineers, cultivating a high-performing and accountable engineering environment.

• Facilitate and drive effective communication and collaboration across analog, verification, layout, packaging, firmware, and test teams to ensure program alignment and rapid progress.

• Define, track, and communicate aggressive schedules, resource plans, and risk mitigation strategies, providing clear escalation paths to executive leadership and stakeholders.

• Offer architectural and implementation guidance for complex digital subsystems, such as multi-lane data paths, advanced clocking schemes, and critical mixed-signal control loops.

• Champion design automation, streamlined methodologies, and knowledge-sharing initiatives to optimize the delivery of high-quality silicon within tight timelines.

📝 Enhancement Note: The responsibilities clearly delineate a focus on both technical execution and team leadership. The emphasis on "Execution Ownership & Speed" and "Right-First-Time Delivery" highlights the critical need for process optimization and risk management within the ASIC development cycle. The inclusion of "Program Leadership" and "Cross-Functional Alignment" points to the necessity of strong communication and stakeholder management skills, essential for managing complex, multi-disciplinary projects common in advanced semiconductor development.

🎓 Skills & Qualifications

Education: While not explicitly stated, a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field is typically expected for this level of ASIC development and management.

Experience: Minimum of 10+ years in digital ASIC development, with a demonstrated track record of successfully completing at least 3 full product cycles from specification through to high-volume production. This includes hands-on experience in leading complex digital subsystem designs.

Required Skills:

• Proven track record of driving on-time, first-time-right delivery of complex, high-performance ASICs with mixed-signal interfaces (e.g., SerDes, DACs/ADCs, RF SoCs, display/camera pipelines).

• Strong expertise in RTL design using SystemVerilog and Verilog.

• Proficient in Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) analysis and mitigation.

• Expertise in Static Timing Analysis (STA), logic synthesis, and Place & Route (P&R) methodologies.

• Familiarity with power intent specifications (UPF/CPF) for low-power design.

• Solid understanding and application of DFT/DFD methodologies for testability and debug.

• Deep understanding of mixed-signal interaction challenges, including coupling, jitter, and supply noise, with the ability to effectively collaborate with analog teams on specification splits.

• Demonstrated success in line management, including hiring, mentoring, performance reviews, and career development for engineering teams.

• Proven ability in fast-paced, cross-functional program leadership, managing schedules, risks, and vendor/foundry relationships.

Preferred Skills:

• Experience with specific high-speed interface IP such as PCIe, DDR, or Ethernet.

• Familiarity with scripting languages for automation (e.g., Python, Perl, Tcl).

• Experience with ASIC tape-out and silicon bring-up activities.

• Knowledge of advanced packaging technologies and their impact on digital design.

📝 Enhancement Note: The required skills are highly specific to the ASIC design lifecycle. The emphasis on "10+ years" and "at least 3 full product cycles" indicates a senior role requiring significant practical, hands-on experience. The combination of technical depth in digital design tools and methodologies with strong "line management" and "program leadership" experience is crucial. The mention of specific mixed-signal interfaces like SerDes and DACs/ADCs points to the complex nature of OLIX's ASICs and the need for engineers who can bridge the gap between digital and analog domains.

📊 Process & Systems Portfolio Requirements

Portfolio Essentials:

• Demonstrate a portfolio showcasing successful ASIC development projects, with a focus on the digital subsystems you have personally led or significantly contributed to.

• Provide detailed case studies of complex digital designs, highlighting your role in architecture, implementation, verification handoff, and achieving performance targets.

• Include examples of process improvements or innovative methodologies implemented to enhance execution speed, quality, or efficiency in ASIC development.

Process Documentation:

• Candidates are expected to detail their experience in defining and documenting design flows, verification methodologies, and DFT strategies.

• Portfolio entries should illustrate how processes were established to ensure "first-time-right" silicon delivery, including specific examples of verification coverage and sign-off criteria.

• Documentation examples demonstrating collaboration with cross-functional teams (e.g., analog, layout, firmware) for seamless integration and issue resolution are highly valued.

• Evidence of experience in tracking and reporting on key project metrics, such as schedule adherence, bug counts, and performance benchmarks, is essential.

📝 Enhancement Note: For a role of this seniority in ASIC design management, a portfolio is critical. It should not only showcase technical achievements but also demonstrate leadership in process definition and execution. The emphasis on "first-time-right delivery" and "execution speed" implies that candidates should be prepared to show how they have optimized development workflows and managed complex projects to successful tape-out and production. Experience with documentation for internal processes, design specifications, and project status reports will be highly beneficial.

💵 Compensation & Benefits

Salary Range:

The provided salary range is £220,000+ annually. This is a competitive figure for a senior ASIC Digital Design Manager role in the UK, reflecting the significant experience and leadership required. The "plus" indicates potential for higher compensation based on the candidate's specific qualifications, extensive experience, and demonstrated impact.

Benefits:

• Equity & Ownership: Meaningful stock options, providing a direct stake in OLIX's success.

• Proximity Bonus: An annual "Living-Local Bonus" of £24,000 for employees residing within 20 minutes of the Bristol office, incentivizing local presence and reducing commute time.

• Time Off: 33 days of paid time off (PTO) per year, including UK public holidays.

• Healthcare Coverage: Multiple high-quality medical plan options, including comprehensive family coverage.

• Health Savings Account (HSA): Available with a high-deductible medical option, funded by the company.

• Dental & Vision: Comprehensive dental and vision coverage.

• Additional Coverage: Life insurance, short-term disability, and long-term disability insurance.

• Wellbeing Support: Access to mental health resources, fertility, and family-building support services.

• Commuter Benefits: Pre-tax benefits for commuting and parking expenses.

• Retirement: Access to a 401(k) retirement plan (note: this is US terminology, likely a UK equivalent like a pension scheme with employer match will be offered, e.g., a company pension plan with a 4% employer contribution).

• Employer Match: A 4% employer match on retirement contributions.

• Financial Advisor Access: Employees have access to a dedicated financial advisor for retirement planning and portfolio selection.

• Visa Sponsorship: Full UK and international visa sponsorship is provided for eligible candidates.

• Seamless Relocation: Funding and concierge support from a dedicated relocation partner for national and international moves.

Working Hours:

While a standard 40-hour work week is implied by the mention of 40 hours, the role's demanding nature, focus on "execution speed," and "aggressive schedule targets" suggest that flexibility and potentially longer hours may be required during critical project phases. The company does provide chef-prepared meals if working late, indicating an understanding of demanding work periods.

📝 Enhancement Note: The salary is explicitly stated as £220,000+, which is a significant compensation package for a management role in the UK semiconductor industry. The "Living-Local Bonus" is a unique perk designed to encourage local residency. The mention of a "401(k)" is likely a placeholder or oversight, as UK employees would typically have a pension scheme. The overall benefits package is comprehensive, aiming to support employee well-being, financial security, and ease of relocation, reflecting a global talent acquisition strategy.

🎯 Team & Company Context

🏢 Company Culture

Industry: OLIX operates within the cutting-edge semiconductor industry, specifically focusing on AI hardware acceleration. Their innovation centers around the "OLIX Decode Accelerator 1 (DX-1)," a new paradigm in chip architecture designed to address the infrastructure gap created by the rapid growth of AI. This positions OLIX as a disruptor in a rapidly evolving and highly competitive market.

Company Size: While not explicitly stated in the provided data, the mention of a "team of 6-12 digital engineers" and the sophistication of the product suggest OLIX is likely a well-funded startup or a rapidly growing, specialized technology company rather than a large, established corporation. This implies a dynamic, fast-paced environment where individual contributions have a significant impact.

Founded: The founding date is not provided, but the company's focus on next-generation AI hardware and its ambitious mission to create "the most important company of the next decade" indicates a relatively young, forward-thinking organization.

Team Structure:

• The digital design team comprises 6-12 engineers, reporting to this ASIC Digital Design Manager.

• This manager will be a key technical leader, likely reporting to a Director of Engineering or CTO, and will collaborate closely with leads from analog design, verification, physical design, packaging, firmware, and test engineering.

Methodology:

• OLIX emphasizes a "culture of speed and quality," driving design automation, streamlined methodologies, and knowledge sharing to deliver high-quality silicon on tight timelines.

• Data-driven decision-making is implicit, given the complex nature of ASIC development and the need for rigorous verification and performance analysis.

• Process optimization is a key focus, aiming for "execution speed" and "first-time-right delivery" to minimize development cycles and costs.

Company Website: https://www.olix.com

📝 Enhancement Note: OLIX's description positions them as innovators in AI hardware, tackling a significant infrastructure challenge. The "culture of speed and quality" is a critical differentiator for candidates. The team structure implies a collaborative, yet execution-focused environment, common in high-growth tech companies. The "Living-Local Bonus" suggests a commitment to their Bristol presence.

📈 Career & Growth Analysis

Operations Career Level: This role represents a senior engineering management position within the ASIC development domain. It requires a blend of deep technical expertise in digital design and significant leadership experience in managing teams and complex projects from inception through to mass production. The scope includes not only technical direction but also people management, strategic planning, and cross-functional alignment.

Reporting Structure: The ASIC Digital Design Manager will likely report to a higher-level engineering director or VP of Engineering. They will manage a team of digital design engineers and will need to collaborate extensively with leads and engineers from other critical functions, including analog design, verification, physical implementation, packaging, firmware, and test engineering.

Operations Impact: The impact of this role is profound. Successful delivery of OLIX's next-generation ASICs is central to the company's mission and market position. This role directly influences the company's ability to meet aggressive schedules, achieve product performance targets, and ultimately capture market share in the rapidly growing AI hardware sector. The quality and efficiency of the digital subsystems designed under this manager's leadership will be critical to the overall success and economic viability of OLIX's products.

Growth Opportunities:

• Technical Specialization: Deepen expertise in advanced ASIC architectures, high-speed interfaces, or mixed-signal co-design, potentially leading to Principal Engineer or Architect roles within specialized domains.

• Leadership Advancement: Progress to Director or VP of Engineering roles, overseeing larger engineering organizations, multiple product lines, or entire R&D functions.

• Cross-Functional Expertise: Develop broader knowledge across analog, verification, and systems engineering, enabling a move into broader engineering management or Chief Technology Officer (CTO) track positions.

• Strategic Contribution: Play a key role in shaping OLIX's long-term technology roadmap and product strategy, influencing critical business decisions.

📝 Enhancement Note: This is a pivotal leadership role with clear pathways for both technical and managerial growth. The emphasis on "full product cycles" and "high-volume production" suggests that candidates who excel here will be well-positioned for broader leadership responsibilities within a scaling technology company. The opportunity to significantly impact a company aiming to be a major player in AI hardware is a substantial growth driver.

🌐 Work Environment

Office Type: The role is on-site in Bristol, UK. The description mentions a focus on deep focus and provides specific resources like high-spec noise-cancelling headphones and ergonomic workstations, indicating an environment designed for concentrated engineering work. The availability of chef-prepared meals for late-night work suggests a supportive culture for demanding project phases.

Office Location(s): The primary office location is Bristol, England, United Kingdom. The "Living-Local Bonus" specifically targets employees within a 20-minute commute of this office, reinforcing Bristol as the central hub.

Workspace Context:

• Collaborative Environment: While designed for deep focus, the role necessitates extensive cross-functional collaboration. The workspace is likely set up to facilitate both individual deep work and team interactions, with meeting rooms and common areas.

• Operations Tools & Technology: Employees are provided with M4 Macs as standard, with M4 Pro upgrades available for engineering teams. This indicates a commitment to providing high-performance computing resources essential for complex ASIC design tasks. High-spec noise-cancelling headphones and ergonomic workstations are also provided.

• Team Interaction: The expectation for seamless collaboration suggests frequent interaction with team members and other engineering groups. This might involve regular stand-ups, design reviews, and problem-solving sessions.

Work Schedule: A standard 40-hour work week is implied. However, given the emphasis on "aggressive schedule targets" and "execution speed" in ASIC development, candidates should anticipate the need for flexibility and potentially extended hours during critical project milestones (e.g., pre-tape-out, silicon bring-up). The provision of meals for late work supports this.

📝 Enhancement Note: OLIX is investing in creating a conducive work environment for its engineering team, blending individual focus with collaborative needs. The provision of high-end hardware and ergonomic setups underscores their commitment to employee productivity and well-being. The Bristol location is central, and the "Living-Local Bonus" further emphasizes its importance.

📄 Application & Portfolio Review Process

Interview Process:

• Initial Screening: A review of your resume and any initial application materials, focusing on experience with ASIC development, management, and specific technical skills.

• Technical/Managerial Interview: A discussion with hiring managers or senior engineers to assess your technical depth in digital ASIC design, RTL, synthesis, timing, DFT, and your experience in managing engineering teams. Expect questions on your approach to problem-solving, process improvement, and team development.

• Portfolio Presentation: Candidates will likely be asked to present specific projects from their portfolio that demonstrate their leadership, technical contributions, and ability to deliver complex ASICs. This is a critical stage to showcase "first-time-right" successes and process optimization efforts.

• Cross-Functional Interviews: Interviews with leads from other engineering disciplines (e.g., analog, verification, firmware) to evaluate your ability to collaborate effectively and understand cross-functional dependencies.

• Executive/Final Interview: A discussion with senior leadership to assess cultural fit, strategic thinking, and overall leadership potential within OLIX.

Portfolio Review Tips:

• Highlight Leadership & Impact: For each project, clearly articulate your role, the team size and structure, and your specific contributions to design, schedule, and quality. Quantify your impact with metrics where possible (e.g., schedule improvements, bug reduction).

• Showcase Process Ownership: Present examples of how you have defined, implemented, or improved design processes. Focus on how you've driven "execution speed" and "first-time-right delivery."

• Demonstrate Technical Depth: Be prepared to discuss technical challenges encountered in your projects, the solutions you implemented, and the trade-offs you made, especially concerning mixed-signal interactions.

• Illustrate Cross-Functional Collaboration: Use case studies to show how you've effectively worked with analog, verification, firmware, and layout teams to achieve project goals.

• Focus on Production Success: Emphasize projects that have successfully gone through "tape-out" and reached "high-volume production."

Challenge Preparation:

• Process Design Scenario: Be prepared for a scenario where you might be asked to outline the process for developing a specific digital subsystem or improving an existing design flow to meet aggressive timelines.

• Team Management Scenario: Expect questions about how you would handle performance issues within your team, resolve conflicts between engineers, or onboard new team members.

• Technical Problem-Solving: Be ready to discuss how you would approach a complex technical challenge, such as a difficult timing closure issue or unexpected behavior during silicon bring-up.

📝 Enhancement Note: The interview process will heavily weigh both technical acumen and leadership capabilities. A strong portfolio is essential, serving as tangible evidence of past successes and process improvements. Candidates should prepare to articulate their management philosophy and demonstrate their ability to navigate the complexities of ASIC development in a fast-paced environment.

🛠 Tools & Technology Stack

Primary Tools:

• RTL Design: SystemVerilog, Verilog.

• Synthesis: Tools like Synopsys Design Compiler or Cadence Genus.

• Timing Analysis (STA): Tools like Synopsys PrimeTime or Cadence Tempus.

• Physical Implementation (P&R): Tools from vendors like Cadence (Innovus) or Synopsys (IC Compiler).

• Power Intent: UPF/CPF specification and associated tools for power-aware design.

• DFT/DFD: Design-for-Test and Design-for-Debug tools and methodologies.

Analytics & Reporting:

• Project Management Software: Tools for schedule tracking, resource planning, and risk management (e.g., Jira, Asana, MS Project).

• Version Control Systems: Git for managing RTL code and design documentation.

• Simulation/Verification Tools: While the role is management, an understanding of verification environments (e.g., UVM) and simulators (e.g., Synopsys VCS, Cadence Xcelium) is beneficial for collaboration.

CRM & Automation:

• EDA Tool Suites: Proficiency with comprehensive Electronic Design Automation (EDA) tool suites from major vendors like Cadence and Synopsys.

• Scripting & Automation: Experience with scripting languages (e.g., Python, Perl, Tcl) for automating design flows, verification tasks, and data analysis.

📝 Enhancement Note: Proficiency with industry-standard EDA tools from vendors like Synopsys and Cadence is a baseline requirement for this role. The emphasis on automation implies that candidates who can leverage scripting languages to streamline workflows will be highly valued. While this is a management role, a strong understanding of the tools used by their team and collaborating departments is crucial for effective leadership and problem-solving.

👥 Team Culture & Values

Operations Values:

• Speed & Execution: A core value is delivering high-quality silicon at an accelerated pace, driven by efficient processes and a proactive approach to problem-solving.

• Quality & First-Time-Right: An unwavering commitment to design robustness, rigorous verification, and silicon success to minimize costly re-spins and production delays.

• Collaboration & Alignment: Fostering a culture where teams work in lockstep, with open communication and shared understanding across disciplines to achieve common goals.

• Accountability & Ownership: Each team member is expected to take ownership of their work, meet commitments, and contribute to the collective success of the project and company.

• Innovation & Continuous Improvement: Encouraging new ideas, exploring advanced technologies, and constantly seeking ways to optimize methodologies and enhance performance.

Collaboration Style:

• Integrated Teams: The culture promotes the integration of diverse engineering disciplines, encouraging proactive communication and joint problem-solving between digital, analog, verification, layout, firmware, and test teams.

• Knowledge Sharing: Emphasis on sharing best practices, lessons learned, and technical expertise across the team and wider organization to accelerate learning and development.

• Feedback Loops: A constructive environment for providing and receiving feedback, essential for rapid iteration and process refinement in a fast-paced development cycle.

📝 Enhancement Note: OLIX's culture appears to be a dynamic blend of high-performance expectations and collaborative support. The emphasis on "speed and quality" is paramount, requiring a management style that balances aggressive timelines with rigorous engineering practices. The focus on integrated teams suggests a proactive approach to breaking down siloes between engineering disciplines.

⚡ Challenges & Growth Opportunities

Challenges:

• Aggressive Schedules: Meeting demanding timelines for complex ASIC development in a rapidly evolving AI hardware market requires exceptional project management and risk mitigation skills.

• Mixed-Signal Integration Complexity: Successfully managing the interplay between high-speed digital subsystems and sensitive analog/mixed-signal blocks presents significant technical challenges that require deep understanding and robust collaboration.

• Talent Acquisition & Retention: In the competitive semiconductor industry, attracting and retaining top engineering talent, especially for specialized roles like ASIC design management, can be a continuous challenge.

• Rapid Technological Evolution: Staying abreast of advancements in AI, semiconductor technology, and EDA tools necessitates continuous learning and adaptation of methodologies.

Learning & Development Opportunities:

• Advanced ASIC Architecture: Opportunities to work on cutting-edge ASIC designs for AI acceleration, gaining exposure to novel architectures and high-performance computing challenges.

• Leadership Development: Formal and informal training programs to enhance people management, strategic planning, and executive communication skills, preparing for broader leadership roles.

• Industry Exposure: Potential to attend industry conferences, engage with foundry partners, and stay at the forefront of semiconductor technology trends.

• Cross-Disciplinary Mastery: Deepen understanding of analog design, verification methodologies, firmware development, and packaging sciences through close collaboration and project involvement.

📝 Enhancement Note: The challenges presented are inherent to a fast-paced, innovative semiconductor company. Overcoming these will require strong leadership, technical acumen, and a proactive approach. The growth opportunities are substantial, offering a chance to make a significant impact on a company poised for growth in a critical technology sector.

💡 Interview Preparation

Strategy Questions:

• "Describe your approach to managing an ASIC development team with aggressive schedule targets. How do you balance speed with quality and ensure first-time-right silicon?" (Focus on process, risk management, and team motivation).

• "Walk me through a complex digital subsystem you managed from specification to tape-out. What were the key challenges, how did you overcome them, and what was the outcome?" (Prepare a detailed case study from your portfolio).

Company & Culture Questions:

• "What interests you most about OLIX and our mission to revolutionize AI hardware?" (Research OLIX's technology and market position; connect your aspirations to their goals).

• "How do you build and maintain a culture of accountability and continuous improvement within an engineering team?" (Discuss your management philosophy, performance management techniques, and feedback mechanisms).

Portfolio Presentation Strategy:

• Structure Your Narrative: For each project, clearly define the problem, your role and team, the solution implemented, the challenges faced, and the quantifiable results (schedule, performance, quality metrics).

• Visualize Your Impact: Use diagrams, charts, and key metrics to illustrate design complexity, process improvements, and project outcomes. Avoid overwhelming slides with text.

• Focus on Leadership & Process: Emphasize your leadership in guiding the team, defining processes, and making critical technical and project management decisions. Highlight how you achieved "first-time-right" delivery.

• Anticipate Technical Deep Dives: Be prepared to answer detailed technical questions about your designs and methodologies, especially regarding mixed-signal interactions and high-speed interfaces.

📝 Enhancement Note: Candidates should prepare to articulate their leadership philosophy and demonstrate how they drive technical excellence and team performance within the demanding context of ASIC development. A well-prepared portfolio and clear, concise answers to strategy and behavioral questions will be key to success.

📌 Application Steps

To apply for this ASIC Digital Design Manager position:

• Submit your application through the provided link on Ashby.

• Portfolio Customization: Tailor your resume and cover letter to highlight your experience in ASIC digital design management, specifically mentioning successful full product cycles, mixed-signal integration, RTL design, synthesis, STA, DFT/DFD, and team leadership. Quantify achievements wherever possible.

• Prepare Your Portfolio: Select 2-3 key projects that best demonstrate your ability to lead digital subsystem delivery, achieve first-time-right silicon, and manage aggressive schedules. Be ready to present these in detail, focusing on your leadership role and process improvements.

• Research OLIX: Familiarize yourself with OLIX's mission, technology (DX-1), and market positioning in AI hardware acceleration. Understand their emphasis on "speed and quality."

• Practice Interview Responses: Prepare answers for common interview questions related to technical expertise, leadership, team management, cross-functional collaboration, and problem-solving, using your experience as examples.

⚠️ Important Notice: This enhanced job description includes AI-generated insights and operations industry-standard assumptions. All details should be verified directly with the hiring organization before making application decisions.