Senior Design Manager

📍 Job Overview

Job Title: Senior Design Manager Company: onsemi Location: Brno, South Moravia, Czech Republic Job Type: Full time Category: Engineering Management / Hardware Design Date Posted: 2026-01-15 Experience Level: 10+ years Remote Status: On-site

🚀 Role Summary

• Lead the architecture, development, and delivery of complex analog and mixed-signal Intellectual Property (IP) blocks, driving innovation in semiconductor design.
• Guide and mentor multi-disciplinary teams, fostering a high-performance culture across design, verification, layout, product engineering, and technology development functions.
• Oversee the creation of high-quality IP solutions suitable for various technology nodes, ensuring alignment with market demands in automotive and industrial sectors.
• Drive strategic initiatives in Non-Volatile Memory (NVM), One-Time Programmable (OTP), or embedded memory architectures, a key preference for this role.
• Contribute to onsemi's mission of building a better future by enabling disruptive innovations in intelligent power and sensing technologies.

📝 Enhancement Note: The raw job description focuses heavily on the technical aspects of analog and mixed-signal IP design management. This enhancement infers a strong emphasis on leadership, strategic direction, and team development, aligning with a "Senior Manager" title and the company's focus on disruptive innovation in high-growth markets like automotive and industrial. The preference for NVM/OTP/embedded memory experience suggests a specialization within the analog domain.

📈 Primary Responsibilities

• Architect, design, and develop complex analog and mixed-signal IP blocks, ensuring robust performance and adherence to specifications.
• Lead and manage cross-functional teams, including analog design engineers, verification engineers, layout engineers, and product engineering specialists, throughout the entire IP development lifecycle.
• Define and drive the technical roadmap for analog and mixed-signal IP, with a particular focus on Non-Volatile Memory (NVM), OTP, or embedded memory solutions.
• Oversee the verification, characterization, and validation of IP blocks to ensure high quality, reliability, and performance across multiple technology nodes.
• Collaborate closely with technology development teams to evaluate and implement new process technologies, optimizing IP for performance, power, and area.
• Work with product engineering to define test strategies, characterize silicon, and ensure successful product integration and ramp-up.
• Provide technical leadership and mentorship to team members, fostering their professional growth and technical expertise.
• Manage project timelines, resources, and budgets effectively to ensure on-time and on-budget delivery of IP projects.
• Engage with product marketing and business units to understand market requirements and translate them into technical specifications for new IP development.
• Drive continuous improvement initiatives in design methodologies, tools, and processes to enhance efficiency and product quality.

📝 Enhancement Note: The primary responsibilities have been detailed to reflect the typical scope of a Senior Design Manager in a semiconductor company. This includes not only technical leadership in IP development but also team management, strategic planning, cross-functional collaboration, and project execution, all critical for a senior-level role.

🎓 Skills & Qualifications

Education:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. A Ph.D. is a plus.
• Advanced coursework in analog circuit design, mixed-signal design, semiconductor physics, and memory technologies.

Experience:

• Minimum of 10 years of progressive experience in analog and mixed-signal IC design.
• Proven track record of successfully leading complex IP development projects from concept to silicon validation.
• Experience in managing and mentoring engineering teams, with demonstrated leadership capabilities.

Required Skills:

• Deep expertise in analog circuit design principles and methodologies (e.g., amplifiers, data converters, power management ICs, PLLs).
• Strong understanding of mixed-signal design flows, including simulation, verification, and layout aspects.
• Proven experience in IP architecture definition and development.
• Proficiency with industry-standard EDA tools for analog/mixed-signal simulation, layout, and verification (e.g., Cadence Virtuoso, Spectre, HSpice, Synopsys).
• Experience with technology development and process integration for semiconductor manufacturing.
• Excellent leadership, communication, and interpersonal skills to effectively manage teams and collaborate with stakeholders.
• Ability to define and drive technical strategy and roadmaps for IP development.
• Experience with product engineering, silicon characterization, and test methodologies.

Preferred Skills:

• Direct experience with Non-Volatile Memory (NVM), One-Time Programmable (OTP), or embedded memory architectures.
• Familiarity with memory design principles, including sense amplifiers, write circuits, and peripheral logic.
• Experience in designing for automotive and/or industrial applications, understanding their specific requirements (e.g., AEC-Q100, ISO 26262).
• Knowledge of advanced semiconductor technologies and their implications for analog/mixed-signal IP.
• Experience with scripting languages (e.g., Perl, Python, Tcl) for automation of design and verification tasks.
• Understanding of system-level design and integration challenges.

📝 Enhancement Note: The skills and qualifications have been expanded to include specific technical tools and methodologies common in semiconductor IP design management, as well as leadership and strategic competencies expected for a senior role. The preference for NVM/OTP/embedded memory experience has been integrated as a preferred skill.

📊 Process & Systems Portfolio Requirements

Portfolio Essentials:

• Demonstrated examples of complex analog and mixed-signal IP blocks designed and delivered.
• Case studies showcasing leadership in guiding teams through the entire design cycle, from architecture to silicon validation.
• Documentation or presentations detailing IP architecture choices, design trade-offs, and performance justifications.
• Evidence of managing cross-functional teams and ensuring successful IP integration into larger chip designs.
• Examples of contributions to process improvement initiatives within design teams.

Process Documentation:

• Ability to define and document robust design flows for analog and mixed-signal IP, including verification and layout methodologies.
• Experience in creating and maintaining detailed technical documentation for IP blocks, including specifications, design reports, and user guides.
• Familiarity with version control systems (e.g., Git) for managing design files and documentation.
• Understanding of quality management systems and their application in semiconductor IP development.
• Documentation of experience with memory architecture design, if applicable, detailing key circuits and operational principles.

📝 Enhancement Note: For a Senior Design Manager role, a portfolio would typically showcase not just individual technical contributions but also leadership in team processes, project management, and successful IP delivery. This section emphasizes the need to demonstrate management of complex design cycles and cross-functional team collaboration.

💵 Compensation & Benefits

Salary Range: For a Senior Design Manager role with 10+ years of experience in Brno, Czech Republic, the estimated annual gross salary range is typically between €90,000 and €140,000. This range can vary based on specific experience, the depth of NVM/memory expertise, and the overall compensation structure of onsemi.

Benefits:

• Comprehensive health insurance coverage for employees and dependents.
• Life insurance and disability benefits.
• Generous paid time off, including vacation days, sick leave, and public holidays.
• Retirement savings plan or pension contributions.
• Opportunities for professional development, including training, conferences, and further education.
• Relocation assistance may be available for qualified candidates.
• Employee stock purchase plans or stock options.
• Access to onsemi's global network of expertise and cutting-edge technology.
• Company-sponsored events and team-building activities.
• Potential for performance-based bonuses and salary increases.

Working Hours:

• Standard full-time employment, typically around 40 hours per week.
• Flexibility may be offered, with core working hours to facilitate team collaboration, but on-site presence is expected.
• Occasional overtime may be required to meet project deadlines.

📝 Enhancement Note: Salary estimation for Brno, Czech Republic, was based on industry benchmarks for senior engineering management roles in the semiconductor sector, considering the cost of living and typical compensation packages. Benefits are standard for a large, multinational technology company, with emphasis on professional growth and long-term security.

🎯 Team & Company Context

🏢 Company Culture

Industry: Semiconductor Manufacturing, Electronics, Technology. onsemi is a key player in the semiconductor industry, focusing on disruptive innovations for automotive and industrial end-markets. This means a culture that values forward-thinking, problem-solving, and a commitment to enabling megatrends like vehicle electrification, sustainable energy, and industrial automation. Company Size: Large Enterprise (onsemi has over 30,000 employees globally). This size indicates a stable, well-established organization with structured processes, global reach, and significant resources for R&D and employee development. It also implies opportunities for cross-departmental collaboration and career advancement within a large framework. Founded: 1999 (as ON Semiconductor). The company has a solid history and evolution in the semiconductor space, demonstrating resilience and adaptability in a rapidly changing technological landscape.

Team Structure:

• The role likely sits within a broader Hardware Engineering or IP Development department.
• The Senior Design Manager will lead a dedicated team of analog/mixed-signal designers, verification engineers, layout specialists, and potentially product engineers focused on specific IP domains, such as memory or power management.
• This team will report through a Director or Vice President of Engineering.
• Collaboration will be extensive with other engineering teams (digital design, system engineering), product management, marketing, and technology development groups.

Methodology:

• Data-Driven Decision Making: Emphasis on using simulation results, characterization data, and performance metrics to guide design choices and optimize IP.
• Agile/Iterative Development: While semiconductor design has long cycles, agile principles may be applied to manage sprints within larger project phases, especially for verification and IP integration.
• Cross-Functional Collaboration: Strong emphasis on communication and teamwork between design, verification, layout, product engineering, and technology development to ensure seamless IP delivery.
• Quality First Approach: A deep commitment to delivering high-quality, reliable IP that meets stringent automotive and industrial standards.

Company Website: https://www.onsemi.com/

📝 Enhancement Note: The company context has been enriched by referencing onsemi's specific market focus (automotive, industrial) and its stated mission. The team structure and methodology reflect typical practices in large semiconductor firms, emphasizing collaboration and data-driven approaches.

📈 Career & Growth Analysis

Operations Career Level: Senior Management. This position signifies a leadership role responsible for a critical function (IP Design) within the engineering organization. It involves strategic input, team development, and accountability for significant project outcomes. The candidate is expected to contribute not just technically but also in shaping the team's direction and capabilities.

Reporting Structure: The Senior Design Manager will typically report to an Engineering Director or VP of Engineering. They will, in turn, manage a team of engineers, potentially including lead engineers or architects who manage smaller sub-teams or specific technical areas. This structure allows for clear lines of responsibility and strategic alignment from top-level management down to individual contributors.

Operations Impact: The IP blocks developed under this management are foundational to onsemi's semiconductor products. High-quality, efficient, and innovative analog/mixed-signal IP directly impacts the performance, power consumption, and cost of the final chips. This, in turn, affects the competitiveness and success of onsemi's offerings in high-growth markets like electric vehicles, industrial automation, and advanced connectivity (5G, cloud infrastructure). The manager's leadership directly influences the company's ability to deliver cutting-edge solutions and maintain its market position.

Growth Opportunities:

• Technical Specialization: Deepen expertise in advanced NVM/memory technologies or other critical analog/mixed-signal domains, potentially becoming a recognized expert or principal architect.
• Organizational Leadership: Progress to higher management roles, such as Director of Engineering or VP of R&D, with broader responsibilities across multiple teams or departments.
• Strategic Planning: Contribute to corporate-level technology roadmapping, M&A evaluations, or strategic partnerships within the semiconductor ecosystem.
• Global Mobility: Opportunities to work in other onsemi R&D centers globally, leading diverse international teams.
• Cross-Functional Roles: Transition into roles focused on product line management, technology strategy, or business unit leadership, leveraging deep technical and market understanding.

📝 Enhancement Note: The career analysis focuses on the progression and impact typical for a Senior Manager in a technology firm, emphasizing both technical depth and organizational leadership. The "Operations" keyword is used here to align with the prompt's request for operations roles, interpreting "Operations" broadly to include the operational execution of engineering management.

🌐 Work Environment

Office Type: Corporate R&D facility. The Brno location is a significant R&D hub for onsemi, suggesting a modern, well-equipped office environment designed for engineering and innovation. It will likely feature collaborative workspaces, private offices for management, meeting rooms, and potentially specialized labs. Office Location(s): Brno, Czech Republic. This location offers a strategic base in Central Europe, providing access to a skilled engineering talent pool and a central position within the European market. Workspace Context:

• Collaborative Spaces: Ample meeting rooms, breakout areas, and open-plan zones designed to encourage spontaneous interaction and problem-solving among team members.
• Advanced Tools and Technology: Access to state-of-the-art EDA tools, high-performance computing clusters for simulations, and potentially lab equipment for silicon bring-up and characterization.
• Team Interaction: A culture that promotes regular team meetings, design reviews, and cross-functional sync-ups to ensure alignment and efficient workflow. The on-site nature means direct, in-person collaboration is the norm.
• Professional Setting: A professional atmosphere that fosters innovation, accountability, and a focus on achieving engineering excellence.

Work Schedule:

• The standard work schedule is typically Monday to Friday, aligning with a full-time employment status.
• While core hours are expected for team synchronization, there may be some flexibility to accommodate individual work styles and personal needs, provided project deliverables are met.
• Given the nature of managing complex projects and global teams, occasional work outside standard hours might be necessary to coordinate with colleagues in different time zones or meet critical project milestones.

📝 Enhancement Note: The work environment description is tailored to a large semiconductor R&D center, emphasizing the tools, collaborative spaces, and professional atmosphere conducive to complex engineering work. The on-site requirement is highlighted.

📄 Application & Portfolio Review Process

Interview Process:

• Initial Screening: HR or recruiter call to assess basic qualifications, experience, and cultural fit.
• Hiring Manager Interview: In-depth discussion with the hiring manager (likely a Director or VP) focusing on leadership experience, strategic thinking, team management philosophy, and technical depth in analog/mixed-signal design.
• Technical Deep Dive: Interviews with senior engineers or architects on the team to assess technical expertise, problem-solving skills, and familiarity with specific design areas (e.g., memory, power management). May include whiteboard exercises or detailed discussion of past projects.
• Cross-Functional Stakeholder Interviews: Meetings with peers from related departments (e.g., verification, product engineering, technology development) to evaluate collaboration skills and understanding of the broader product development ecosystem.
• Portfolio Presentation/Case Study: A session where the candidate presents a significant IP development project they led, detailing architecture, challenges, team management, and outcomes. This is crucial for demonstrating practical leadership and technical acumen.
• Final Interview: Potentially with a senior executive for final approval, focusing on strategic alignment and long-term vision.

Portfolio Review Tips:

• Focus on Leadership: Highlight your role in guiding the team, defining the strategy, and overcoming obstacles. Quantify team achievements and project successes.
• Technical Depth: Be prepared to discuss the technical challenges, design trade-offs, and innovative solutions implemented in the presented projects.
• Process & Methodology: Explain the design flows, verification strategies, and project management methodologies used. Showcase how you improved processes or efficiency.
• Impact & Results: Clearly articulate the impact of your team's work on the final product and the business, using metrics where possible (e.g., performance improvements, cost reductions, time-to-market).
• NVM/Memory Relevance: If you have NVM/OTP/embedded memory experience, ensure at least one case study strongly features this expertise.
• Conciseness and Clarity: Present complex information in a clear, structured, and engaging manner.

Challenge Preparation:

• Technical Challenge: Be ready for problems related to analog circuit design, mixed-signal integration, or memory architecture. Practice problem-solving on a whiteboard.
• Leadership Scenario: Prepare for behavioral questions about managing difficult team members, resolving conflicts, motivating engineers, and handling project setbacks.
• Strategic Thinking: Consider how you would approach developing a new IP roadmap, evaluating new technologies, or improving team efficiency.
• NVM/Memory Specifics: If applying with this specialization, be prepared to discuss specific challenges and solutions in NVM/OTP/embedded memory design and integration.

📝 Enhancement Note: This section provides detailed, actionable advice for preparing for the interview and portfolio presentation, specifically tailored for a Senior Design Manager role in a semiconductor company, with an emphasis on the preferred memory expertise.

🛠 Tools & Technology Stack

Primary Tools:

• EDA Suites: Cadence Virtuoso (schematic, layout, simulation), Spectre (analog simulation), HSpice (transistor-level simulation), PSpice (circuit simulation).
• Verification Tools: Synopsys VCS/QuestaSim (for mixed-signal verification, if applicable), potentially specialized memory verification environments.
• Layout Tools: Cadence Virtuoso Layout Suite, Synopsys IC Compiler (for digital aspects of mixed-signal).
• Scripting & Automation: Python, Perl, Tcl for automating repetitive tasks, data analysis, and flow control.

Analytics & Reporting:

• Simulation Data Analysis: Tools like Cadence ADE, Synopsys CustomSim Explorer, or custom scripts for analyzing large simulation result files.
• Performance Metrics Tools: Custom reporting scripts or integration with internal tools to track key performance indicators (KPIs) for IP blocks (e.g., speed, power, area, noise).
• Project Management Software: Tools like JIRA, Confluence, or internal systems for task tracking, progress reporting, and documentation.

CRM & Automation:

• Version Control: Git, Perforce, or similar systems for managing design files and ensuring design integrity.
• Data Management: Internal databases or cloud storage solutions for managing IP libraries, design specifications, and test results.
• Collaboration Platforms: Microsoft Teams, Slack, or internal company platforms for team communication and knowledge sharing.

📝 Enhancement Note: The tools and technology stack are specific to analog and mixed-signal IC design and management in the semiconductor industry. This includes essential EDA tools, verification environments, and project management/collaboration platforms.

👥 Team Culture & Values

Operations Values:

• Innovation & Excellence: A drive to push the boundaries of technology and deliver best-in-class IP that enables next-generation products.
• Collaboration & Teamwork: Strong emphasis on working together across disciplines and geographies to achieve common goals, fostering a supportive and inclusive environment.
• Accountability & Ownership: Taking responsibility for the entire lifecycle of IP development, from conception to silicon, ensuring quality and timely delivery.
• Customer Focus: Understanding and meeting the needs of internal (product teams) and external (automotive, industrial) customers through high-performance, reliable solutions.
• Continuous Improvement: A commitment to learning, adapting, and enhancing design processes, methodologies, and technical skills.

Collaboration Style:

• Proactive Communication: Encouraging open and frequent communication through regular team meetings, design reviews, and informal discussions.
• Cross-Functional Synergy: Building strong working relationships with verification, layout, product engineering, and technology development teams to ensure seamless project execution.
• Knowledge Sharing: Promoting an environment where engineers share insights, best practices, and lessons learned to elevate the collective expertise of the team.
• Constructive Feedback: Fostering a culture where feedback is given and received constructively, leading to continuous improvement in both individual performance and team processes.

📝 Enhancement Note: The team culture and values are inferred based on typical large semiconductor companies that emphasize innovation, collaboration, and quality, aligning with onsemi's market focus and mission.

⚡ Challenges & Growth Opportunities

Challenges:

• Complexity of Analog/Mixed-Signal Design: Managing intricate designs with demanding performance, power, and area constraints across multiple technology nodes.
• NVM/Memory Integration: Navigating the specific challenges of designing and integrating reliable and efficient Non-Volatile Memory or embedded memory IP, which can be sensitive to process variations.
• Team Leadership & Motivation: Effectively leading and motivating a diverse team of highly skilled engineers, fostering collaboration, and managing performance.
• Rapid Technological Advancement: Keeping pace with the evolving semiconductor landscape, new process technologies, and emerging market demands.
• Global Team Coordination: Managing and aligning teams that may be distributed across different geographical locations and time zones.

Learning & Development Opportunities:

• Advanced Technical Training: Access to specialized courses and workshops in cutting-edge analog design techniques, memory architectures, and new semiconductor technologies.
• Leadership Development Programs: Participation in onsemi's internal leadership training, executive coaching, and mentorship programs.
• Industry Conferences & Forums: Opportunities to attend and present at leading semiconductor and design conferences (e.g., ISSCC, VLSI Symposium, DAC) to stay abreast of industry trends and network.
• Cross-Disciplinary Exposure: Gaining deeper understanding of other areas such as digital design, system-level integration, and product marketing through collaborative projects.
• Mentorship: Being mentored by senior leaders within onsemi or acting as a mentor to junior engineers, fostering leadership skills.

📝 Enhancement Note: Challenges and growth opportunities are framed within the context of advanced semiconductor design management and leadership development, with specific mention of NVM/memory integration challenges.

💡 Interview Preparation

Strategy Questions:

• "Describe a time you led a team through a complex analog/mixed-signal IP development cycle. What were the key challenges, your approach, and the outcome?" (Focus on leadership, problem-solving, and results).
• "How would you architect a new embedded memory IP block for a high-volume automotive application, considering performance, power, and reliability trade-offs?" (Assess technical strategy and domain knowledge).
• "Walk me through a situation where your team faced a significant technical roadblock. How did you guide them to a solution?" (Evaluate problem-solving and team guidance).
• "What is your philosophy on managing and developing engineering talent? How do you foster a high-performance culture?" (Assess leadership and people management skills).
• "How do you ensure the quality and reliability of IP blocks, especially for safety-critical applications like automotive?" (Focus on quality processes and domain awareness).

Company & Culture Questions:

• "Based on your understanding, how does onsemi's focus on automotive and industrial markets influence its IP development strategy?" (Demonstrate research and strategic alignment).
• "How would you integrate your team's work with other departments, such as verification, layout, and product engineering, to ensure efficient product delivery?" (Assess collaboration and process understanding).
• "What are your expectations regarding onsemi's company culture, and how do you contribute to a positive and productive work environment?" (Gauge cultural fit and self-awareness).

Portfolio Presentation Strategy:

• Structure: Begin with an overview of the IP block, its purpose, and the target market. Then, detail the architecture, key design challenges, your leadership role, team contributions, solutions implemented, and final silicon results/impact.
• Metrics: Quantify achievements with data – e.g., "achieved 15% lower power consumption than previous generation," "met timing targets with 20% margin," "reduced verification time by 30% through automation."
• NVM/Memory Focus: If presenting a memory IP, clearly articulate the specific design choices for memory cells, sense amplifiers, write circuits, and peripheral logic, and how these addressed performance, endurance, or retention requirements.
• Leadership Narrative: Weave your leadership actions throughout the presentation – how you mentored engineers, made critical technical decisions, managed risks, and facilitated team collaboration.
• Q&A Readiness: Anticipate detailed technical and managerial questions and prepare concise, informed answers.

📝 Enhancement Note: Interview preparation advice is highly specific, providing example questions and detailed strategies for portfolio presentation, directly relevant to a Senior Design Manager role with NVM/memory expertise.

📌 Application Steps

To apply for this Senior Design Manager position:

• Submit your application through the provided link on the onsemi careers portal.
• Customize Your Resume: Tailor your resume to highlight your leadership experience, success in managing analog/mixed-signal IP development, and any specific experience with NVM, OTP, or embedded memory architectures. Use keywords from the job description.
• Prepare Your Portfolio: Curate 1-2 key projects that best showcase your leadership, technical expertise, and successful IP delivery. Be ready to present these in detail, focusing on your role, team management, technical challenges, and quantifiable results.
• Research onsemi: Understand onsemi's strategic focus on automotive and industrial markets, its key product areas, and its mission. Prepare to discuss how your skills and experience align with the company's goals.
• Practice Interview Responses: Rehearse answers to common behavioral and technical interview questions, particularly those related to leadership, team management, and analog/mixed-signal design challenges. Practice your portfolio presentation.

⚠️ Important Notice: This enhanced job description includes AI-generated insights and operations industry-standard assumptions. All details should be verified directly with the hiring organization before making application decisions.