Physical Design Manager

📍 Job Overview

Job Title: Physical Design Manager

Company: Astera Labs

Location: Israel

Job Type: Full-time

Category: Engineering / Semiconductor / Management

Date Posted: February 09, 2026

Experience Level: 10+ years

Remote Status: On-site

🚀 Role Summary

• Lead the establishment and growth of a new R&D center in Israel focused on AI infrastructure connectivity solutions.

• Drive the end-to-end physical design (RTL-to-GDS) strategy for complex semiconductor chips, targeting advanced process nodes (5nm, 3nm, and below).

• Build, mentor, and manage a high-performing ASIC Backend team, fostering a culture of technical excellence and innovation.

• Collaborate cross-functionally with Architecture, Design, DFT, and Product teams to achieve aggressive Power Performance Area (PPA) targets.

• Define and implement cutting-edge physical design methodologies and flows to ensure silicon meets extreme performance and power requirements for hyperscale AI deployments.

📝 Enhancement Note: This role is for a foundational member of a new R&D site in Israel, requiring significant leadership in building a team and establishing processes from scratch. The focus on AI infrastructure connectivity and advanced nodes (5nm, 3nm and below) indicates a strategic importance for Astera Labs' future growth and competitive positioning in the AI hardware market.

📈 Primary Responsibilities

• Team Leadership & Development:

  • Recruit, onboard, and develop a team of skilled physical design engineers in Israel.
  • Provide technical guidance, mentorship, and performance management to the backend team.
  • Foster a collaborative and high-performance team environment.
  • Manage and lead external contractors and global partners to ensure seamless project execution and delivery.

• Physical Implementation & Methodology:

  • Own and drive the complete RTL-to-GDS flow, including synthesis, floorplanning, place & route (P&R), clock tree synthesis (CTS), power/clock distribution, and timing/physical signoff.
  • Establish and refine advanced physical design methodologies for leading-edge process technologies.
  • Conduct feasibility studies for new architectures and drive Quality of Results (QoR) optimization to meet PPA targets.
  • Oversee power integrity (PI) and signal integrity (SI) analysis and ensure robust power and clock delivery networks.

• Cross-Functional Collaboration & Technical Excellence:

  • Partner closely with chip architecture, digital design, DFT, and product engineering teams to align on design specifications and PPA goals.

  • Address complex technical challenges related to signal integrity, thermal management, and power delivery in high-speed connectivity silicon.

  • Manage integration of complex macro-level designs, subsystem components, and full-chip implementation.

  • Contribute to the evaluation of foundry process nodes and third-party IP selection.

📝 Enhancement Note: The responsibilities highlight a blend of people management, technical execution, and strategic methodology development, typical for a leadership role establishing a new engineering function. The emphasis on "cutting-edge methodologies" and "advanced process nodes" indicates an expectation for innovation and expertise in the latest semiconductor technologies.

🎓 Skills & Qualifications

Education:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a closely related technical field.

Experience:

• 10+ years of progressive, hands-on experience in Physical Design/ASIC Backend engineering within the semiconductor industry.

Required Skills:

• Deep expertise in end-to-end RTL-to-GDS flows, including synthesis, floorplanning, place & route (P&R), clock tree synthesis (CTS), power/clock distribution, and timing/physical signoff.

• Mastery of industry-standard EDA tools for physical design, such as Synopsys Fusion Compiler/ICC2, Cadence Innovus, and related tools for Static Timing Analysis (STA), physical verification (DRC/LVS), and formal verification.

• Proven experience working with advanced process technologies (e.g., 5nm, 3nm, and below) and understanding their unique challenges.

• Strong understanding of low-power implementation techniques and flows (UPF/CPF).

• Experience with full-chip design, including managing both macro-level and subsystem-level integration.

• Excellent problem-solving skills with a "can-do" attitude and a strong drive for results.

Preferred Skills:

• Deep understanding of Power & Noise analysis, including Electro-Migration (EM) and IR Drop analysis.

• Experience with Design for Test (DFT) integration and its impact on physical design.

• Background or familiarity with high-speed interfaces and data center protocols such as PCIe, CXL, and Ethernet.

• Experience in evaluating foundry process nodes and selecting/integrating third-party Intellectual Property (IP).

📝 Enhancement Note: The "10+ years" experience, coupled with the requirement for leadership and advanced process technology expertise, positions this as a senior management role. The explicit mention of specific EDA tools (Synopsys, Cadence) is crucial for ATS screening and indicates the expected toolchain proficiency.

📊 Process & Systems Portfolio Requirements

Portfolio Essentials:

• Demonstrable experience in leading complex physical design projects from RTL to GDS, showcasing successful tape-outs on advanced nodes.

• Case studies detailing specific challenges and innovative solutions implemented in floorplanning, P&R, CTS, and timing/physical signoff.

• Examples of methodology development or flow optimization that resulted in significant PPA improvements or reduced cycle time.

• Documentation or presentation materials that illustrate proficiency in managing cross-functional dependencies and stakeholder communication during the physical design process.

Process Documentation:

• Ability to document and standardize RTL-to-GDS flows for a new R&D site.

• Experience in creating clear guidelines for P&R, STA, and signoff procedures, ensuring consistency and quality across the team.

• Documentation of methodology for Power Performance Area (PPA) optimization, including feasibility studies and QoR improvement strategies.

• Process for managing external contractors and global teams to ensure alignment with internal methodologies and project timelines.

📝 Enhancement Note: For a management role, the portfolio isn't just about individual technical contributions but also about demonstrating leadership in process definition, team building, and successful project execution. Candidates should be prepared to discuss their experience in establishing best practices and managing complex projects with a team.

💵 Compensation & Benefits

Salary Range:

Given the senior management level, specialized skill set in advanced semiconductor physical design, and the strategic importance of establishing a new R&D center in Israel, the estimated annual salary range for a Physical Design Manager in Israel would likely fall between ₪450,000 to ₪700,000+ (Israeli New Shekels). This range is based on typical compensation for senior engineering management roles in the high-tech sector in Israel, considering factors like experience, leadership responsibilities, and the highly competitive nature of AI/semiconductor talent.

Benefits:

• Comprehensive health insurance coverage (medical, dental, vision).

• Competitive stock options or Restricted Stock Units (RSUs) as part of the compensation package, reflecting the company's public status (NASDAQ: ALAB).

• Generous paid time off (vacation, sick leave, holidays).

• Retirement savings plan (e.g., pension fund contributions).

• Professional development opportunities, including training, conferences, and advanced certifications.

• Potential for relocation assistance if applicable.

• Access to cutting-edge technology and the opportunity to work on impactful AI infrastructure projects.

Working Hours:

• Standard full-time working hours are typically around 40 hours per week, Monday to Friday.

• Given the nature of managing a global team and critical R&D projects, flexibility may be required, potentially including occasional work outside of standard hours to accommodate global collaboration or project deadlines.

📝 Enhancement Note: Salary estimates for Israel are based on market research for senior engineering management roles in leading tech companies, taking into account the high cost of living and demand for specialized talent in the region. Stock options are a common component for publicly traded tech companies like Astera Labs.

🎯 Team & Company Context

🏢 Company Culture

Industry: Semiconductor / AI Infrastructure / Connectivity Solutions. Astera Labs operates at the intersection of AI hardware and data center infrastructure, providing critical connectivity solutions that enable large-scale AI deployments. This positions them as a key enabler for the rapidly growing AI market.

Company Size: Astera Labs is a publicly traded company (NASDAQ: ALAB) with a significant and growing presence. While specific employee numbers for the new Israel center are not detailed, the company is substantial enough to establish international R&D hubs, indicating a growth-oriented and well-funded organization.

Founded: Astera Labs was founded in 2017. This means it's a relatively young, dynamic company that has achieved significant milestones, including going public, at a rapid pace, suggesting agility and a strong market fit.

Team Structure:

• The Physical Design team in Israel will be part of a larger global R&D organization.

• This role involves building a local team in Israel, which will report to the Physical Design Manager.

• Close collaboration is expected with other engineering disciplines (Architecture, Design, DFT, Product) both within the Israel center and with teams in other locations.

Methodology:

• Data-Driven Decision Making: Expect a strong emphasis on data analysis for PPA optimization, performance tuning, and issue resolution.

• Agile Development: While not explicitly stated, the fast-paced nature of AI and semiconductor development often implies agile methodologies for project management and execution.

• Process Optimization: A core aspect of this role is defining and continuously improving physical design flows and methodologies.

• Collaborative Problem Solving: The company fosters collaboration across teams and geographies to tackle complex technical challenges.

Company Website: www.asteralabs.com

📝 Enhancement Note: Astera Labs' focus on AI infrastructure and its recent IPO suggest a high-growth, innovative environment. The establishment of an R&D center in Israel indicates a strategic commitment to global talent acquisition and expanding its engineering capabilities.

📈 Career & Growth Analysis

Operations Career Level: This role represents a senior-level management position within the engineering organization. It's a critical leadership role responsible for building and leading a core technical function for a new R&D site. This is beyond a senior individual contributor role and encompasses strategic planning, team development, and technical oversight.

Reporting Structure: The Physical Design Manager will likely report to a Director or VP of Engineering, overseeing a team of physical design engineers and potentially contractors. They will be a key technical leader within the Israel R&D center and a crucial interface with global engineering teams.

Operations Impact: The success of this role directly impacts Astera Labs' ability to deliver cutting-edge semiconductor products that power AI infrastructure. Effective physical design is fundamental to achieving the performance, power, and cost targets required for hyperscale data centers, thus directly influencing the company's market competitiveness and revenue potential.

Growth Opportunities:

• Leadership Expansion: Potential to grow the Israel R&D center's engineering capabilities, taking on broader management responsibilities for additional teams or functions.

• Strategic Influence: Contribute to the overall R&D strategy and technology roadmap for Astera Labs' connectivity solutions.

• Technical Specialization: Deepen expertise in advanced process technologies, AI hardware, and high-speed interconnects, becoming a recognized expert in the field.

• Cross-Functional Leadership: Opportunities to lead cross-functional initiatives that span design, verification, and product engineering.

• Mentorship and Talent Development: Play a key role in shaping the next generation of semiconductor engineers in Israel.

📝 Enhancement Note: This is a high-impact role with significant potential for career advancement, particularly due to the greenfield nature of establishing the Israel R&D center. The opportunity to shape a team and strategy from inception is a major draw for experienced leaders.

🌐 Work Environment

Office Type: The role is based in a new R&D center in Israel, which will likely be a modern, collaborative office environment designed to foster innovation and teamwork. This will include state-of-the-art lab facilities and engineering workstations.

Office Location(s): Israel. Specific city not mentioned, but Israel has a vibrant high-tech ecosystem, particularly in areas like Tel Aviv, Haifa, and surrounding regions.

Workspace Context:

• Collaborative Spaces: Expect a mix of private offices for management and dedicated workstations for engineers, alongside meeting rooms and common areas designed for brainstorming and collaboration.

• Technology Rich: Access to advanced EDA tools, high-performance computing resources for simulations and place & route, and robust IT infrastructure will be essential.

• Global Interaction: The work environment will necessitate seamless communication and collaboration with teams across different time zones, likely utilizing video conferencing and collaboration platforms.

• Focus on Innovation: The culture is expected to be driven by innovation, problem-solving, and a commitment to pushing the boundaries of AI hardware.

Work Schedule:

• The standard work week is typically Monday to Friday.

• Given the global nature of the teams and the critical deadlines in semiconductor development, flexibility might be required, including occasional work outside standard hours to accommodate meetings with international colleagues or to meet project milestones.

📝 Enhancement Note: The description implies a modern, tech-focused workspace designed for collaboration and innovation, typical of leading semiconductor companies establishing new R&D hubs.

📄 Application & Portfolio Review Process

Interview Process:

1. Initial Screening: HR or Recruiter call to assess basic qualifications, experience, and cultural fit.

2. Hiring Manager Interview: In-depth discussion with the hiring manager (likely a Director/VP of Engineering) focusing on leadership experience, team-building philosophy, strategic approach to physical design, and understanding of the company's mission.

3. Technical Interviews: Series of interviews with senior engineers and potential team members covering:

• Deep technical expertise in RTL-to-GDS flows, EDA tools, advanced process nodes, PPA optimization, STA, and physical verification.
• Problem-solving scenarios related to complex physical design challenges.
• Methodology development and implementation experience.

1. Cross-Functional Interviews: Discussions with leads from Architecture, Design, DFT, or Product teams to assess collaboration skills and understanding of the broader chip development lifecycle.

2. Management/Leadership Assessment: Further evaluation of leadership style, team management strategies, and ability to build and motivate a new team. This may involve behavioral questions and case studies related to team development.

3. Final Round/Executive Interview: Potentially with senior leadership to discuss overall vision, strategic alignment, and long-term goals for the Israel R&D center.

Portfolio Review Tips:

• Highlight Leadership: Focus on projects where you led teams, mentored engineers, and drove successful outcomes. Quantify team size, project complexity, and results achieved.

• Demonstrate Methodology Expertise: Prepare specific examples of how you established or improved physical design flows, methodologies, or tool usage. Show the impact of these improvements (e.g., PPA gains, schedule acceleration).

• Showcase Technical Depth: Be ready to discuss intricate technical challenges you've overcome in areas like timing closure, power integrity, signal integrity, and physical verification on advanced nodes.

• Quantify Impact: Whenever possible, use metrics to demonstrate the success of your projects and leadership. For example, "Achieved timing closure with X% margin," or "Reduced P&R runtime by Y% through methodology improvements."

• Explain Strategic Decisions: Be prepared to discuss why certain tools, flows, or approaches were chosen for specific projects and the trade-offs involved.

• Case Studies: Prepare 2-3 detailed case studies covering:

  • Building a team or establishing a new function.
  • Solving a complex physical design challenge on an advanced node.

Challenge Preparation:

• Methodology Design Challenge: You might be asked to outline a proposed RTL-to-GDS flow for a hypothetical complex chip on a 3nm process, including key tools, stages, checks, and PPA optimization strategies.

• Leadership Scenario: Behavioral questions about managing difficult team members, resolving conflicts, motivating engineers, or handling project setbacks.

• Technical Problem-Solving: Hypothetical scenarios involving timing violations, power issues, or DRC/LVS failures on advanced nodes, and how you would diagnose and resolve them.

• Strategic Planning: Questions about how you would prioritize tasks for a new team, manage resources, and align with global engineering efforts.

📝 Enhancement Note: The interview process for a management role at this level will heavily assess leadership capabilities, strategic thinking, and the ability to build and manage a team in a new environment, in addition to deep technical expertise. Candidates should prepare to speak extensively about their leadership experience and strategic approach.

🛠 Tools & Technology Stack

Primary Tools:

• Physical Design Suites: Synopsys Fusion Compiler, Synopsys IC Compiler II (ICC2), Cadence Innovus. Proficiency in at least one of these is critical.

• Static Timing Analysis (STA): Synopsys PrimeTime, Cadence Tempus Timing Signoff.

• Physical Verification: Synopsys IC Validator, Cadence Pegasus, Mentor Graphics Calibre (for DRC, LVS, ERC).

• Power Analysis: Synopsys PrimePower, Cadence Voltus IC Power Integrity Solution.

• Signal Integrity: Synopsys Integrated Field Solver, Cadence Sigrity.

• Floorplanning & CTS: Tools integrated within the P&R suites.

• Low Power Design: UPF/CPF implementation tools and methodologies.

Analytics & Reporting:

• While specific tools aren't listed, expect to use tools that generate reports on timing, power, physical verification, and PPA metrics.

• Familiarity with scripting languages (e.g., TCL, Python, Perl) for automating tool flows and data analysis is highly beneficial.

CRM & Automation:

• Not directly applicable to the core physical design role, but collaboration tools like Jira, Confluence, or internal project management systems will be used for task tracking and documentation.

• Version control systems (e.g., Git) might be used for managing design files and scripts.

• Automation scripts for running EDA tools, parsing results, and generating reports are essential.

📝 Enhancement Note: The explicit mention of Synopsys and Cadence tools is a strong indicator of the expected EDA toolchain. Candidates must be proficient with these industry-standard tools for advanced node physical design.

👥 Team Culture & Values

Operations Values:

• Innovation & Excellence: A drive to push the boundaries of AI infrastructure connectivity through cutting-edge semiconductor design.

• Collaboration: Strong emphasis on teamwork across disciplines and geographies to solve complex problems.

• Ownership & Accountability: Taking full responsibility for the success of the physical design process and the quality of delivered silicon.

• Data-Driven Approach: Utilizing data and rigorous analysis to make informed decisions and optimize designs.

• Continuous Improvement: A commitment to refining methodologies, improving flows, and fostering a learning environment.

Collaboration Style:

• Cross-Functional Integration: Close partnerships with Architecture, RTL Design, DFT, and Verification teams are paramount. Regular sync-ups and joint problem-solving sessions are expected.

• Global Teamwork: Effective communication and coordination with engineering teams in other regions will be key, requiring clear documentation and proactive engagement.

• Mentorship & Knowledge Sharing: A culture where senior engineers mentor junior team members, and knowledge is shared openly to elevate the entire team's capabilities.

• Feedback Culture: Openness to constructive feedback to drive continuous improvement in both individual performance and team processes.

📝 Enhancement Note: The culture is likely to be fast-paced, technically demanding, and highly collaborative, reflecting the nature of a rapidly growing, innovation-driven semiconductor company focused on a critical market like AI.

⚡ Challenges & Growth Opportunities

Challenges:

• Building a New Team: Establishing a high-performing physical design team from scratch in a new location, including recruitment, onboarding, and team integration.

• Advanced Node Complexity: Navigating the intricate challenges of physical design at 5nm, 3nm, and below, which involve complex process variations, power delivery, and signal integrity issues.

• Global Coordination: Effectively managing and collaborating with teams in different time zones and potentially different organizational cultures.

• PPA Optimization: Meeting aggressive Power, Performance, and Area targets for high-speed connectivity chips in the demanding AI hyperscale environment.

• Methodology Development: Defining and implementing cutting-edge flows that are efficient, robust, and scalable for future projects.

Learning & Development Opportunities:

• Deep Expertise in Advanced Nodes: Gaining unparalleled experience with the latest semiconductor manufacturing processes and their design implications.

• Leadership Development: Honing management and strategic leadership skills in a high-growth, international environment.

• Cutting-Edge Technology: Working at the forefront of AI hardware, contributing to technologies that will power the next generation of artificial intelligence.

• Industry Exposure: Potential to attend industry conferences, engage with foundry partners, and stay abreast of the latest trends in physical design and AI infrastructure.

• Mentorship: Opportunities to mentor and develop junior engineers, contributing to the growth of semiconductor talent in Israel.

📝 Enhancement Note: This role presents significant challenges, particularly in building a team and mastering advanced node design, but these challenges are directly tied to substantial growth and learning opportunities.

💡 Interview Preparation

Strategy Questions:

• "Describe your approach to building a high-performing physical design team from the ground up in a new location." (Focus on recruitment strategy, onboarding, culture building, and initial team structure.)

• "How would you establish cutting-edge RTL-to-GDS methodologies for 3nm process technology at a new R&D site?" (Discuss tool selection, flow definition, PPA optimization strategies, and signoff criteria.)

• "Imagine a critical timing violation is found late in the signoff phase on a complex high-speed interface. How would you diagnose and resolve this issue, considering potential impacts on PPA and schedule?" (Demonstrate systematic problem-solving, understanding of STA, and trade-off analysis.)

Company & Culture Questions:

• "What excites you about Astera Labs' mission to enable AI infrastructure through connectivity solutions?" (Show genuine interest in the company's market and technology.)

• "How do you foster a culture of innovation and continuous improvement within an engineering team?" (Provide examples of initiatives you've led or supported.)

• "Describe your experience working with global teams. What are the key challenges and how do you overcome them?" (Show adaptability and cross-cultural awareness.)

Portfolio Presentation Strategy:

• Structure: Organize your portfolio around key projects, using a STAR (Situation, Task, Action, Result) or similar methodology for clarity.

• Highlight Leadership: For each relevant project, emphasize your role in leading the team, defining strategy, and driving execution.

• Quantify Results: Use numbers and metrics extensively to showcase PPA improvements, schedule adherence, team growth, and successful tape-outs.

• Methodology Focus: Dedicate sections to explain methodologies you've developed or implemented, detailing the process, tools, and benefits.

• Advanced Node Expertise: Clearly articulate your experience with specific advanced nodes (5nm, 3nm, etc.) and the unique challenges encountered and overcome.

• Visuals: Use diagrams, charts, and graphs where appropriate to illustrate complex designs, flows, or results.

• Conciseness: Be prepared to provide a high-level overview quickly, then dive into details as requested.

Challenge Preparation:

• Be ready to discuss hypothetical scenarios related to physical design challenges, team management, and process development.

• Practice articulating your thought process clearly and logically.

• Prepare to whiteboard solutions or flow diagrams.

• Think about how you would balance competing priorities (e.g., schedule vs. PPA, performance vs. power).

📝 Enhancement Note: Preparation should focus on demonstrating not just technical prowess but also strong leadership, strategic thinking, and the ability to build and manage a team in a new, dynamic environment.

📌 Application Steps

To apply for this Physical Design Manager position:

• Submit your application through the Astera Labs careers portal via the provided Greenhouse link.

• Tailor Your Resume: Ensure your resume clearly highlights your 10+ years of physical design experience, leadership roles, expertise in advanced process nodes (5nm, 3nm+), proficiency with industry-standard EDA tools (Synopsys, Cadence), and experience with RTL-to-GDS flows, STA, and PPA optimization. Use keywords from the job description.

• Prepare Your Portfolio: Curate examples of successful physical design projects, focusing on your leadership contributions, methodology development, PPA results, and experience with advanced nodes. Be ready to present 2-3 detailed case studies that showcase your capabilities.

• Research Astera Labs: Understand the company's mission, products (AI infrastructure, connectivity solutions), recent IPO, and its strategic expansion into Israel. This will help you tailor your answers to demonstrate alignment with their goals and culture.

• Practice Interview Responses: Prepare for technical, behavioral, and situational questions, particularly those related to team building, methodology development, and solving complex physical design challenges. Rehearse presenting your portfolio and case studies.

⚠️ Important Notice: This enhanced job description includes AI-generated insights and operations industry-standard assumptions. All details should be verified directly with the hiring organization before making application decisions.